Simulation Results: hmac

 
28/04/2026 15:30:29 DVSim: v1.32.0 sha: f8cd0a3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.97 %
  • code
  • 98.01 %
  • assert
  • 96.70 %
  • func
  • 45.20 %
  • line
  • 99.74 %
  • branch
  • 99.67 %
  • cond
  • 96.51 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 9.510s 351.088us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.780s 32.355us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.730s 46.424us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 4.200s 1909.825us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.400s 209.413us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.440s 43.470us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.730s 46.424us 1 1 100.00
hmac_csr_aliasing 2.400s 209.413us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 39.940s 12515.938us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 43.190s 994.388us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 9.210s 343.069us 1 1 100.00
hmac_test_sha384_vectors 447.410s 60760.852us 1 1 100.00
hmac_test_sha512_vectors 373.990s 42686.935us 1 1 100.00
hmac_test_hmac256_vectors 6.290s 189.863us 1 1 100.00
hmac_test_hmac384_vectors 9.580s 743.928us 1 1 100.00
hmac_test_hmac512_vectors 8.540s 246.561us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 14.040s 1036.482us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 351.710s 3224.847us 1 1 100.00
error 1 1 100.00
hmac_error 84.100s 13009.358us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 87.250s 39599.802us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 9.510s 351.088us 1 1 100.00
hmac_long_msg 39.940s 12515.938us 1 1 100.00
hmac_back_pressure 43.190s 994.388us 1 1 100.00
hmac_datapath_stress 351.710s 3224.847us 1 1 100.00
hmac_burst_wr 14.040s 1036.482us 1 1 100.00
hmac_stress_all 733.130s 30992.907us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 9.510s 351.088us 1 1 100.00
hmac_long_msg 39.940s 12515.938us 1 1 100.00
hmac_back_pressure 43.190s 994.388us 1 1 100.00
hmac_datapath_stress 351.710s 3224.847us 1 1 100.00
hmac_wipe_secret 87.250s 39599.802us 1 1 100.00
hmac_test_sha256_vectors 9.210s 343.069us 1 1 100.00
hmac_test_sha384_vectors 447.410s 60760.852us 1 1 100.00
hmac_test_sha512_vectors 373.990s 42686.935us 1 1 100.00
hmac_test_hmac256_vectors 6.290s 189.863us 1 1 100.00
hmac_test_hmac384_vectors 9.580s 743.928us 1 1 100.00
hmac_test_hmac512_vectors 8.540s 246.561us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 9.510s 351.088us 1 1 100.00
hmac_long_msg 39.940s 12515.938us 1 1 100.00
hmac_back_pressure 43.190s 994.388us 1 1 100.00
hmac_datapath_stress 351.710s 3224.847us 1 1 100.00
hmac_burst_wr 14.040s 1036.482us 1 1 100.00
hmac_error 84.100s 13009.358us 1 1 100.00
hmac_wipe_secret 87.250s 39599.802us 1 1 100.00
hmac_test_sha256_vectors 9.210s 343.069us 1 1 100.00
hmac_test_sha384_vectors 447.410s 60760.852us 1 1 100.00
hmac_test_sha512_vectors 373.990s 42686.935us 1 1 100.00
hmac_test_hmac256_vectors 6.290s 189.863us 1 1 100.00
hmac_test_hmac384_vectors 9.580s 743.928us 1 1 100.00
hmac_test_hmac512_vectors 8.540s 246.561us 1 1 100.00
hmac_stress_all 733.130s 30992.907us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 733.130s 30992.907us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.670s 21.692us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.690s 12.814us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.540s 129.046us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.540s 129.046us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.780s 32.355us 1 1 100.00
hmac_csr_rw 0.730s 46.424us 1 1 100.00
hmac_csr_aliasing 2.400s 209.413us 1 1 100.00
hmac_same_csr_outstanding 1.380s 57.624us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.780s 32.355us 1 1 100.00
hmac_csr_rw 0.730s 46.424us 1 1 100.00
hmac_csr_aliasing 2.400s 209.413us 1 1 100.00
hmac_same_csr_outstanding 1.380s 57.624us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.030s 74.548us 1 1 100.00
hmac_tl_intg_err 3.500s 282.636us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 3.500s 282.636us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 9.510s 351.088us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 2.340s 41.592us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 128.030s 6654.345us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.780s 152.597us 1 1 100.00