Simulation Results: i2c

 
28/04/2026 15:30:29 DVSim: v1.32.0 sha: f8cd0a3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.48 %
  • code
  • 82.08 %
  • assert
  • 96.19 %
  • func
  • 81.18 %
  • line
  • 96.51 %
  • branch
  • 92.55 %
  • cond
  • 85.83 %
  • toggle
  • 89.66 %
  • FSM
  • 45.83 %
Validation stages
V1
100.00%
V2
92.68%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 21.320s 3834.204us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 5.770s 2146.668us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 0.920s 177.993us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 0.820s 47.261us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 2.070s 63.629us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 1.560s 42.085us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 0.990s 37.886us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 0.820s 47.261us 1 1 100.00
i2c_csr_aliasing 1.560s 42.085us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 1 1 100.00
i2c_host_error_intr 6.920s 490.078us 1 1 100.00
host_stress_all 1 1 100.00
i2c_host_stress_all 3227.150s 92782.463us 1 1 100.00
host_maxperf 1 1 100.00
i2c_host_perf 7.800s 2809.869us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 0.900s 77.736us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 66.780s 3957.260us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 44.790s 5976.094us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 1.010s 1045.167us 1 1 100.00
i2c_host_fifo_fmt_empty 11.620s 678.162us 1 1 100.00
i2c_host_fifo_reset_rx 6.110s 171.764us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 67.820s 14450.785us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 11.050s 3044.727us 1 1 100.00
i2c_host_mode_toggle 0 1 0.00
i2c_host_mode_toggle 0.660s 124.202us 0 1 0.00
target_glitch 0 1 0.00
i2c_target_glitch 2.480s 9871.504us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 15.320s 4853.338us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 4.160s 4887.779us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 5.460s 376.784us 1 1 100.00
i2c_target_intr_smoke 4.270s 3793.843us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 0.960s 294.299us 1 1 100.00
i2c_target_fifo_reset_tx 1.710s 175.073us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 47.360s 44111.909us 1 1 100.00
i2c_target_stress_rd 5.460s 376.784us 1 1 100.00
i2c_target_intr_stress_wr 3.540s 3504.965us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 4.680s 1087.303us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 3.620s 2286.684us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 5.460s 2542.878us 1 1 100.00
target_mode_glitch 0 1 0.00
i2c_target_hrst 20.960s 10039.308us 0 1 0.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 1.010s 846.369us 1 1 100.00
i2c_target_fifo_watermarks_tx 1.360s 518.891us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 7.800s 2809.869us 1 1 100.00
i2c_host_perf_precise 155.530s 6058.178us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 11.050s 3044.727us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 1.900s 80.313us 1 1 100.00
target_mode_nack_generation 3 3 100.00
i2c_target_nack_acqfull 1.870s 1841.583us 1 1 100.00
i2c_target_nack_acqfull_addr 2.400s 526.510us 1 1 100.00
i2c_target_nack_txstretch 1.080s 590.231us 1 1 100.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 4.480s 1007.248us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 2.050s 930.767us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 0.820s 53.203us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 0.820s 17.153us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 1.330s 47.006us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 1.330s 47.006us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 0.920s 177.993us 1 1 100.00
i2c_csr_rw 0.820s 47.261us 1 1 100.00
i2c_csr_aliasing 1.560s 42.085us 1 1 100.00
i2c_same_csr_outstanding 0.960s 251.697us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 0.920s 177.993us 1 1 100.00
i2c_csr_rw 0.820s 47.261us 1 1 100.00
i2c_csr_aliasing 1.560s 42.085us 1 1 100.00
i2c_same_csr_outstanding 0.960s 251.697us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_tl_intg_err 1.660s 515.667us 1 1 100.00
i2c_sec_cm 1.050s 97.232us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 1.660s 515.667us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 9.310s 604.681us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 1.950s 626.936us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 8.350s 359.284us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
i2c_target_glitch 54544981783520003963221944018003496478314650336095674861221295833652361962926 84
UVM_INFO @ 9871504259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
i2c_target_unexp_stop 6507348356514877040906145954252762097056043344453104362619557452106348262300 79
UVM_ERROR @ 626936111 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 626936111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
i2c_target_hrst 10204002236986506877632075292906555994784853388336250643819069135229915159100 79
UVM_INFO @ 10039307995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
i2c_host_stress_all_with_rand_reset 78418866816216694732688274779004823120930709197586351592467552802077174831943 100
UVM_INFO @ 604680759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 42990953554837312320510489534087058218787510180621255794559597966904316590808 86
UVM_INFO @ 359283930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
i2c_host_mode_toggle 95598311743873552043893806047309136218134382402078099907625942074372876156141 81
UVM_INFO @ 124202174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---