Simulation Results: keymgr

 
28/04/2026 15:30:29 DVSim: v1.32.0 sha: f8cd0a3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.28 %
  • code
  • 92.60 %
  • assert
  • 97.49 %
  • func
  • 50.76 %
  • line
  • 98.72 %
  • branch
  • 97.53 %
  • cond
  • 92.60 %
  • toggle
  • 90.44 %
  • FSM
  • 83.72 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_smoke 1.890s 88.467us 1 1 100.00
random 1 1 100.00
keymgr_random 3.140s 305.428us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 1.360s 47.432us 1 1 100.00
csr_rw 1 1 100.00
keymgr_csr_rw 1.250s 102.225us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 18.320s 4098.545us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 3.560s 211.111us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_csr_mem_rw_with_rand_reset 1.650s 197.059us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_csr_rw 1.250s 102.225us 1 1 100.00
keymgr_csr_aliasing 3.560s 211.111us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 1 1 100.00
keymgr_cfg_regwen 22.810s 669.851us 1 1 100.00
sideload 4 4 100.00
keymgr_sideload 2.660s 75.763us 1 1 100.00
keymgr_sideload_kmac 4.400s 296.605us 1 1 100.00
keymgr_sideload_aes 3.620s 760.675us 1 1 100.00
keymgr_sideload_otbn 4.040s 782.805us 1 1 100.00
direct_to_disabled_state 1 1 100.00
keymgr_direct_to_disabled 1.120s 120.292us 1 1 100.00
lc_disable 1 1 100.00
keymgr_lc_disable 1.920s 68.102us 1 1 100.00
kmac_error_response 1 1 100.00
keymgr_kmac_rsp_err 1.650s 46.142us 1 1 100.00
invalid_sw_input 1 1 100.00
keymgr_sw_invalid_input 1.930s 31.264us 1 1 100.00
invalid_hw_input 1 1 100.00
keymgr_hwsw_invalid_input 1.920s 36.324us 1 1 100.00
sync_async_fault_cross 1 1 100.00
keymgr_sync_async_fault_cross 1.320s 55.198us 1 1 100.00
stress_all 1 1 100.00
keymgr_stress_all 0.820s 28.597us 1 1 100.00
intr_test 1 1 100.00
keymgr_intr_test 0.670s 84.937us 1 1 100.00
alert_test 1 1 100.00
keymgr_alert_test 1.080s 40.197us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_tl_errors 1.460s 78.341us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_tl_errors 1.460s 78.341us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_csr_hw_reset 1.360s 47.432us 1 1 100.00
keymgr_csr_rw 1.250s 102.225us 1 1 100.00
keymgr_csr_aliasing 3.560s 211.111us 1 1 100.00
keymgr_same_csr_outstanding 1.620s 689.308us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_csr_hw_reset 1.360s 47.432us 1 1 100.00
keymgr_csr_rw 1.250s 102.225us 1 1 100.00
keymgr_csr_aliasing 3.560s 211.111us 1 1 100.00
keymgr_same_csr_outstanding 1.620s 689.308us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
keymgr_sec_cm 11.200s 2108.860us 1 1 100.00
tl_intg_err 2 2 100.00
keymgr_sec_cm 11.200s 2108.860us 1 1 100.00
keymgr_tl_intg_err 5.090s 806.191us 1 1 100.00
shadow_reg_update_error 1 1 100.00
keymgr_shadow_reg_errors 2.780s 401.937us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
keymgr_shadow_reg_errors 2.780s 401.937us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
keymgr_shadow_reg_errors 2.780s 401.937us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
keymgr_shadow_reg_errors 2.780s 401.937us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
keymgr_shadow_reg_errors_with_csr_rw 4.950s 1160.259us 1 1 100.00
prim_count_check 1 1 100.00
keymgr_sec_cm 11.200s 2108.860us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_sec_cm 11.200s 2108.860us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
keymgr_tl_intg_err 5.090s 806.191us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
keymgr_shadow_reg_errors 2.780s 401.937us 1 1 100.00
sec_cm_op_config_regwen 1 1 100.00
keymgr_cfg_regwen 22.810s 669.851us 1 1 100.00
sec_cm_reseed_config_regwen 2 2 100.00
keymgr_random 3.140s 305.428us 1 1 100.00
keymgr_csr_rw 1.250s 102.225us 1 1 100.00
sec_cm_sw_binding_config_regwen 2 2 100.00
keymgr_random 3.140s 305.428us 1 1 100.00
keymgr_csr_rw 1.250s 102.225us 1 1 100.00
sec_cm_max_key_ver_config_regwen 2 2 100.00
keymgr_random 3.140s 305.428us 1 1 100.00
keymgr_csr_rw 1.250s 102.225us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
keymgr_lc_disable 1.920s 68.102us 1 1 100.00
sec_cm_constants_consistency 1 1 100.00
keymgr_hwsw_invalid_input 1.920s 36.324us 1 1 100.00
sec_cm_intersig_consistency 1 1 100.00
keymgr_hwsw_invalid_input 1.920s 36.324us 1 1 100.00
sec_cm_hw_key_sw_noaccess 1 1 100.00
keymgr_random 3.140s 305.428us 1 1 100.00
sec_cm_output_keys_ctrl_redun 1 1 100.00
keymgr_sideload_protect 2.680s 974.455us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 11.200s 2108.860us 1 1 100.00
sec_cm_data_fsm_sparse 1 1 100.00
keymgr_sec_cm 11.200s 2108.860us 1 1 100.00
sec_cm_ctrl_fsm_local_esc 1 1 100.00
keymgr_sec_cm 11.200s 2108.860us 1 1 100.00
sec_cm_ctrl_fsm_consistency 1 1 100.00
keymgr_custom_cm 3.550s 342.524us 1 1 100.00
sec_cm_ctrl_fsm_global_esc 1 1 100.00
keymgr_lc_disable 1.920s 68.102us 1 1 100.00
sec_cm_ctrl_ctr_redun 1 1 100.00
keymgr_sec_cm 11.200s 2108.860us 1 1 100.00
sec_cm_kmac_if_fsm_sparse 1 1 100.00
keymgr_sec_cm 11.200s 2108.860us 1 1 100.00
sec_cm_kmac_if_ctr_redun 1 1 100.00
keymgr_sec_cm 11.200s 2108.860us 1 1 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 1 1 100.00
keymgr_custom_cm 3.550s 342.524us 1 1 100.00
sec_cm_kmac_if_done_ctrl_consistency 1 1 100.00
keymgr_custom_cm 3.550s 342.524us 1 1 100.00
sec_cm_reseed_ctr_redun 1 1 100.00
keymgr_sec_cm 11.200s 2108.860us 1 1 100.00
sec_cm_side_load_sel_ctrl_consistency 1 1 100.00
keymgr_custom_cm 3.550s 342.524us 1 1 100.00
sec_cm_sideload_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 11.200s 2108.860us 1 1 100.00
sec_cm_ctrl_key_integrity 1 1 100.00
keymgr_custom_cm 3.550s 342.524us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
keymgr_stress_all_with_rand_reset 2.550s 475.200us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
keymgr_stress_all_with_rand_reset 52354549169144957064349675459388418022644986928942103243037600394313136402945 147
UVM_INFO @ 475200440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---