Simulation Results: lc_ctrl/volatile_unlock_disabled

 
28/04/2026 15:30:29 DVSim: v1.32.0 sha: f8cd0a3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.55 %
  • code
  • 82.88 %
  • assert
  • 94.13 %
  • func
  • 91.64 %
  • line
  • 97.21 %
  • branch
  • 93.67 %
  • cond
  • 79.52 %
  • toggle
  • 83.26 %
  • FSM
  • 60.75 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 0.990s 76.174us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.830s 31.530us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.730s 40.017us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.140s 181.161us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.030s 27.957us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.000s 59.032us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.730s 40.017us 1 1 100.00
lc_ctrl_csr_aliasing 1.030s 27.957us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.670s 104.864us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 12.980s 601.663us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.940s 45.430us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.570s 275.648us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.420s 1381.995us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.090s 438.872us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 7.420s 1381.995us 1 1 100.00
lc_ctrl_prog_failure 1.570s 275.648us 1 1 100.00
lc_ctrl_errors 5.090s 438.872us 1 1 100.00
lc_ctrl_security_escalation 5.640s 188.725us 1 1 100.00
lc_ctrl_jtag_state_failure 25.430s 2328.382us 1 1 100.00
lc_ctrl_jtag_prog_failure 6.650s 586.799us 1 1 100.00
lc_ctrl_jtag_errors 68.150s 3696.624us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 7.040s 1551.943us 1 1 100.00
lc_ctrl_jtag_state_post_trans 11.710s 486.676us 1 1 100.00
lc_ctrl_jtag_prog_failure 6.650s 586.799us 1 1 100.00
lc_ctrl_jtag_errors 68.150s 3696.624us 1 1 100.00
lc_ctrl_jtag_access 7.250s 922.130us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 20.350s 3910.223us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.190s 138.569us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.490s 242.661us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 16.020s 936.155us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.310s 256.287us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.790s 54.018us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.570s 1492.143us 1 1 100.00
lc_ctrl_jtag_alert_test 1.130s 567.802us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 2.230s 184.587us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.060s 15.262us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 70.390s 31788.071us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.030s 64.852us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.450s 75.316us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.450s 75.316us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.830s 31.530us 1 1 100.00
lc_ctrl_csr_rw 0.730s 40.017us 1 1 100.00
lc_ctrl_csr_aliasing 1.030s 27.957us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.390s 68.872us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.830s 31.530us 1 1 100.00
lc_ctrl_csr_rw 0.730s 40.017us 1 1 100.00
lc_ctrl_csr_aliasing 1.030s 27.957us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.390s 68.872us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.360s 3063.485us 1 1 100.00
lc_ctrl_tl_intg_err 2.240s 226.544us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.240s 226.544us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 12.980s 601.663us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.420s 1381.995us 1 1 100.00
lc_ctrl_sec_cm 6.360s 3063.485us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.420s 1381.995us 1 1 100.00
lc_ctrl_sec_cm 6.360s 3063.485us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.420s 1381.995us 1 1 100.00
lc_ctrl_sec_cm 6.360s 3063.485us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.420s 1381.995us 1 1 100.00
lc_ctrl_sec_cm 6.360s 3063.485us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.420s 1381.995us 1 1 100.00
lc_ctrl_sec_cm 6.360s 3063.485us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.420s 1381.995us 1 1 100.00
lc_ctrl_sec_cm 6.360s 3063.485us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.420s 1381.995us 1 1 100.00
lc_ctrl_sec_cm 6.360s 3063.485us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.420s 1381.995us 1 1 100.00
lc_ctrl_sec_cm 6.360s 3063.485us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.640s 188.725us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.670s 104.864us 1 1 100.00
lc_ctrl_jtag_state_post_trans 11.710s 486.676us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.400s 311.503us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.400s 311.503us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.170s 184.061us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.110s 1731.468us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.110s 1731.468us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 7.000s 345.540us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 105849202241658651607701840890132388709760893798420650460103486108293049716795 204
UVM_INFO @ 345539660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---