Simulation Results: lc_ctrl/volatile_unlock_enabled

 
28/04/2026 15:30:29 DVSim: v1.32.0 sha: f8cd0a3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.63 %
  • code
  • 84.33 %
  • assert
  • 94.13 %
  • func
  • 93.42 %
  • line
  • 97.06 %
  • branch
  • 93.62 %
  • cond
  • 79.28 %
  • toggle
  • 87.22 %
  • FSM
  • 64.49 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.830s 178.255us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.990s 16.615us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.800s 39.201us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.110s 177.072us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.200s 69.252us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.280s 80.530us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.800s 39.201us 1 1 100.00
lc_ctrl_csr_aliasing 1.200s 69.252us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 5.940s 56.246us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 8.230s 2100.869us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.950s 22.996us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.970s 225.914us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 6.940s 259.340us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 8.780s 783.548us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 6.940s 259.340us 1 1 100.00
lc_ctrl_prog_failure 1.970s 225.914us 1 1 100.00
lc_ctrl_errors 8.780s 783.548us 1 1 100.00
lc_ctrl_security_escalation 5.550s 3200.066us 1 1 100.00
lc_ctrl_jtag_state_failure 57.520s 25360.971us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.020s 634.283us 1 1 100.00
lc_ctrl_jtag_errors 32.810s 1892.826us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 6.440s 1357.949us 1 1 100.00
lc_ctrl_jtag_state_post_trans 11.390s 536.097us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.020s 634.283us 1 1 100.00
lc_ctrl_jtag_errors 32.810s 1892.826us 1 1 100.00
lc_ctrl_jtag_access 4.250s 471.156us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 14.750s 1602.361us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.050s 188.774us 1 1 100.00
lc_ctrl_jtag_csr_rw 0.940s 134.819us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 14.360s 804.807us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.280s 438.658us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.050s 30.349us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.470s 364.165us 1 1 100.00
lc_ctrl_jtag_alert_test 0.830s 25.137us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 5.010s 1052.881us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.860s 39.563us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 87.810s 18266.635us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.010s 31.362us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.310s 160.548us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.310s 160.548us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.990s 16.615us 1 1 100.00
lc_ctrl_csr_rw 0.800s 39.201us 1 1 100.00
lc_ctrl_csr_aliasing 1.200s 69.252us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.700s 84.545us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.990s 16.615us 1 1 100.00
lc_ctrl_csr_rw 0.800s 39.201us 1 1 100.00
lc_ctrl_csr_aliasing 1.200s 69.252us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.700s 84.545us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.370s 119.902us 1 1 100.00
lc_ctrl_tl_intg_err 1.640s 188.941us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.640s 188.941us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 8.230s 2100.869us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 6.940s 259.340us 1 1 100.00
lc_ctrl_sec_cm 5.370s 119.902us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 6.940s 259.340us 1 1 100.00
lc_ctrl_sec_cm 5.370s 119.902us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.940s 259.340us 1 1 100.00
lc_ctrl_sec_cm 5.370s 119.902us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.940s 259.340us 1 1 100.00
lc_ctrl_sec_cm 5.370s 119.902us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 6.940s 259.340us 1 1 100.00
lc_ctrl_sec_cm 5.370s 119.902us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.940s 259.340us 1 1 100.00
lc_ctrl_sec_cm 5.370s 119.902us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.940s 259.340us 1 1 100.00
lc_ctrl_sec_cm 5.370s 119.902us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 6.940s 259.340us 1 1 100.00
lc_ctrl_sec_cm 5.370s 119.902us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.550s 3200.066us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 5.940s 56.246us 1 1 100.00
lc_ctrl_jtag_state_post_trans 11.390s 536.097us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.870s 2199.102us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.870s 2199.102us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.830s 236.200us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.450s 644.713us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.450s 644.713us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 18.300s 6206.045us 1 1 100.00