Simulation Results: otbn

 
28/04/2026 15:30:29 DVSim: v1.32.0 sha: f8cd0a3 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.14 %
  • code
  • 95.28 %
  • assert
  • 89.67 %
  • func
  • 97.46 %
  • block
  • 99.37 %
  • line
  • 99.57 %
  • branch
  • 92.13 %
  • toggle
  • 91.97 %
  • FSM
  • 97.44 %
Validation stages
V1
100.00%
V2
85.71%
V2S
88.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 10.000s 154.115us 1 1 100.00
single_binary 1 1 100.00
otbn_single 9.000s 81.053us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 6.000s 15.091us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 5.000s 38.740us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 9.000s 73.702us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 7.000s 30.530us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 7.000s 34.734us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 5.000s 38.740us 1 1 100.00
otbn_csr_aliasing 7.000s 30.530us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 89.000s 3974.653us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 52.000s 5566.649us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 17.000s 164.155us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 49.000s 140.195us 1 1 100.00
back_to_back 0 1 0.00
otbn_multi 1.758s 0.000us 0 1 0.00
stress_all 1 1 100.00
otbn_stress_all 59.000s 283.426us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 6.000s 34.731us 1 1 100.00
zero_state_err_urnd 0 1 0.00
otbn_zero_state_err_urnd 5.000s 7.637us 0 1 0.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 6.000s 36.203us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 9.000s 20.383us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 4.000s 20.288us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 5.000s 301.172us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 5.000s 301.172us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 6.000s 15.091us 1 1 100.00
otbn_csr_rw 5.000s 38.740us 1 1 100.00
otbn_csr_aliasing 7.000s 30.530us 1 1 100.00
otbn_same_csr_outstanding 4.000s 31.665us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 6.000s 15.091us 1 1 100.00
otbn_csr_rw 5.000s 38.740us 1 1 100.00
otbn_csr_aliasing 7.000s 30.530us 1 1 100.00
otbn_same_csr_outstanding 4.000s 31.665us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 10.000s 81.676us 1 1 100.00
otbn_dmem_err 7.000s 50.517us 1 1 100.00
internal_integrity 3 4 75.00
otbn_alu_bignum_mod_err 10.000s 101.190us 1 1 100.00
otbn_controller_ispr_rdata_err 9.000s 18.263us 1 1 100.00
otbn_mac_bignum_acc_err 9.000s 57.587us 1 1 100.00
otbn_urnd_err 7.000s 8.227us 0 1 0.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 4.000s 27.819us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 7.000s 19.901us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 6.000s 14.474us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 164.000s 3773.307us 1 1 100.00
otbn_tl_intg_err 13.000s 1218.093us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 19.000s 619.071us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 164.000s 3773.307us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 164.000s 3773.307us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 10.000s 154.115us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 7.000s 50.517us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 10.000s 81.676us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 13.000s 1218.093us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 6.000s 34.731us 1 1 100.00
sec_cm_controller_fsm_local_esc 4 5 80.00
otbn_imem_err 10.000s 81.676us 1 1 100.00
otbn_dmem_err 7.000s 50.517us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 7.637us 0 1 0.00
otbn_illegal_mem_acc 4.000s 27.819us 1 1 100.00
otbn_sec_cm 164.000s 3773.307us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 164.000s 3773.307us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 9.000s 81.053us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 10.000s 81.676us 1 1 100.00
otbn_dmem_err 7.000s 50.517us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 7.637us 0 1 0.00
otbn_illegal_mem_acc 4.000s 27.819us 1 1 100.00
otbn_sec_cm 164.000s 3773.307us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 164.000s 3773.307us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 6.000s 34.731us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 10.000s 81.676us 1 1 100.00
otbn_dmem_err 7.000s 50.517us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 7.637us 0 1 0.00
otbn_illegal_mem_acc 4.000s 27.819us 1 1 100.00
otbn_sec_cm 164.000s 3773.307us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 164.000s 3773.307us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 9.000s 81.053us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 5.000s 11.799us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 5.000s 37.882us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 28.000s 204.043us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 28.000s 204.043us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 7.000s 19.539us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 164.000s 3773.307us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 164.000s 3773.307us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 8.000s 227.815us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 164.000s 3773.307us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 164.000s 3773.307us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 6.000s 18.369us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 6.000s 18.369us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 4.000s 9.509us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 9.000s 81.053us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 9.000s 81.053us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 9.000s 81.053us 1 1 100.00
sec_cm_write_mem_integrity 0 1 0.00
otbn_multi 1.758s 0.000us 0 1 0.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 9.000s 81.053us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 9.000s 81.053us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 14.000s 177.118us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 9.000s 81.053us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 164.000s 3773.307us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 130.000s 2273.925us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 6.000s 37.051us 1 1 100.00

Error Messages

   Test seed line log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']
otbn_multi 65593956339952277453299225056757915295081285777442382404897926155931588667581 None
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head
enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize
assert bodysize is not None
^^^^^^^^^^^^^^^^^^^^
AssertionError
ninja: build stopped: subcommand failed.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
UVM_ERROR (cip_base_vseq.sv:1237) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
otbn_stress_all_with_rand_reset 31431129534165005806150458755053270138064949454386859071272295379351845891979 382
UVM_INFO @ 2273924998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.u_otbn_core.u_otbn_rnd.u_xoshiro256pp.xoshiro_q cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
otbn_zero_state_err_urnd 6213326761586261202824616153397685402256419263962191115059037311964531231216 104
UVM_INFO @ 7637390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.edn_urnd_ack cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
otbn_urnd_err 43191427401973929522562389924170692094206643379577125784588072126015373435343 108
UVM_INFO @ 8227446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---