Simulation Results: otp_ctrl

 
28/04/2026 15:30:29 DVSim: v1.32.0 sha: f8cd0a3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.61 %
  • code
  • 76.31 %
  • assert
  • 93.54 %
  • func
  • 68.99 %
  • line
  • 88.57 %
  • branch
  • 82.98 %
  • cond
  • 89.99 %
  • toggle
  • 79.04 %
  • FSM
  • 40.97 %
Validation stages
V1
88.89%
V2
80.00%
V2S
77.78%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.780s 781.820us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 4.570s 586.168us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 1.410s 70.584us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.640s 42.617us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 7.040s 968.995us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 6.630s 2613.634us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.180s 75.009us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.640s 42.617us 1 1 100.00
otp_ctrl_csr_aliasing 6.630s 2613.634us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.340s 39.101us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.200s 48.610us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 12.230s 621.186us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 3.530s 171.931us 1 1 100.00
partition_check 0 2 0.00
otp_ctrl_background_chks 2.450s 155.591us 0 1 0.00
otp_ctrl_check_fail 6.210s 338.893us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 6.820s 739.966us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 6.860s 443.314us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 31.300s 5179.224us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 7.430s 1118.961us 1 1 100.00
otp_ctrl_parallel_lc_esc 5.910s 2401.543us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 11.630s 1308.625us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 4.330s 146.767us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 23.560s 1506.310us 1 1 100.00
stress_all 0 1 0.00
otp_ctrl_stress_all 112.700s 10206.839us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.250s 40.329us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.350s 247.135us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 3.180s 65.556us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 3.180s 65.556us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.410s 70.584us 1 1 100.00
otp_ctrl_csr_rw 1.640s 42.617us 1 1 100.00
otp_ctrl_csr_aliasing 6.630s 2613.634us 1 1 100.00
otp_ctrl_same_csr_outstanding 1.810s 170.163us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.410s 70.584us 1 1 100.00
otp_ctrl_csr_rw 1.640s 42.617us 1 1 100.00
otp_ctrl_csr_aliasing 6.630s 2613.634us 1 1 100.00
otp_ctrl_same_csr_outstanding 1.810s 170.163us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 115.460s 22736.002us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 115.460s 22736.002us 1 1 100.00
otp_ctrl_tl_intg_err 7.440s 778.794us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 115.460s 22736.002us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 115.460s 22736.002us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 7.440s 778.794us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 4.570s 586.168us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 4.570s 586.168us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 115.460s 22736.002us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 115.460s 22736.002us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 115.460s 22736.002us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 115.460s 22736.002us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 115.460s 22736.002us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 115.460s 22736.002us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 115.460s 22736.002us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 115.460s 22736.002us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 115.460s 22736.002us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 115.460s 22736.002us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 115.460s 22736.002us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 115.460s 22736.002us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 115.460s 22736.002us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 115.460s 22736.002us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 115.460s 22736.002us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 5.910s 2401.543us 1 1 100.00
otp_ctrl_sec_cm 115.460s 22736.002us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 5.910s 2401.543us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 5.910s 2401.543us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 5.910s 2401.543us 1 1 100.00
otp_ctrl_macro_errs 4.330s 146.767us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 5.910s 2401.543us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 5.910s 2401.543us 1 1 100.00
otp_ctrl_sec_cm 115.460s 22736.002us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 5.910s 2401.543us 1 1 100.00
otp_ctrl_sec_cm 115.460s 22736.002us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 5.910s 2401.543us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 5.910s 2401.543us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 5.910s 2401.543us 1 1 100.00
otp_ctrl_macro_errs 4.330s 146.767us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 5.910s 2401.543us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 5.910s 2401.543us 1 1 100.00
otp_ctrl_sec_cm 115.460s 22736.002us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 3.530s 171.931us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 6.210s 338.893us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 6.860s 443.314us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 6.860s 443.314us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 6.860s 443.314us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 6.860s 443.314us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 6.860s 443.314us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 4.570s 586.168us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 6.860s 443.314us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 4.570s 586.168us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 115.460s 22736.002us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 6.820s 739.966us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 4.570s 586.168us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 4.570s 586.168us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 4.330s 146.767us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 10.270s 2987.923us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 2.200s 448.405us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1315) [otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_check_error does not trigger!
otp_ctrl_background_chks 77597039965579509066678451942879825714485405443479095142358517435203899281076 881
UVM_INFO @ 155591415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 29573647857021223260479331973446379809054851706645522500078576766578927996220 150143
UVM_INFO @ 10206839259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_*
otp_ctrl_check_fail 65677544008519738694207820956664418714240700207202489896044294262886583566542 4486
UVM_INFO @ 338892959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 103857568881576561237085488774479414820608874036518088783449056614731259380872 5668
UVM_INFO @ 146766925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = *
otp_ctrl_stress_all_with_rand_reset 108698090432528310019715306833557286592465539742324116698134878772578062149403 628
UVM_INFO @ 448405031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_csr_mem_rw_with_rand_reset 107511367934426363945775557354637512340829802230072403196654036217343041895335 98
UVM_INFO @ 75009260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---