Simulation Results: pwrmgr

 
28/04/2026 15:30:29 DVSim: v1.32.0 sha: f8cd0a3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.84 %
  • code
  • 94.40 %
  • assert
  • 96.08 %
  • func
  • 97.03 %
  • line
  • 98.92 %
  • branch
  • 95.42 %
  • cond
  • 93.64 %
  • toggle
  • 90.02 %
  • FSM
  • 94.00 %
Validation stages
V1
100.00%
V2
93.33%
V2S
80.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.760s 29.683us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.770s 28.571us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.810s 20.739us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.680s 330.568us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 1.060s 372.826us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.820s 83.510us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.810s 20.739us 1 1 100.00
pwrmgr_csr_aliasing 1.060s 372.826us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.640s 35.542us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.640s 35.542us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 1.000s 85.220us 1 1 100.00
pwrmgr_lowpower_invalid 0.890s 41.427us 1 1 100.00
reset 1 2 50.00
pwrmgr_reset 1.450s 1000.000us 0 1 0.00
pwrmgr_reset_invalid 0.930s 161.000us 1 1 100.00
main_power_glitch_reset 0 1 0.00
pwrmgr_reset 1.450s 1000.000us 0 1 0.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.990s 234.058us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.680s 165.953us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.880s 102.816us 1 1 100.00
stress_all 1 1 100.00
pwrmgr_stress_all 3.470s 2189.002us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.640s 34.563us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.600s 467.939us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.600s 467.939us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.770s 28.571us 1 1 100.00
pwrmgr_csr_rw 0.810s 20.739us 1 1 100.00
pwrmgr_csr_aliasing 1.060s 372.826us 1 1 100.00
pwrmgr_same_csr_outstanding 0.690s 209.410us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.770s 28.571us 1 1 100.00
pwrmgr_csr_rw 0.810s 20.739us 1 1 100.00
pwrmgr_csr_aliasing 1.060s 372.826us 1 1 100.00
pwrmgr_same_csr_outstanding 0.690s 209.410us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
pwrmgr_tl_intg_err 0.680s 14.985us 0 1 0.00
pwrmgr_sec_cm 0.840s 29.573us 0 1 0.00
prim_count_check 0 1 0.00
pwrmgr_sec_cm 0.840s 29.573us 0 1 0.00
prim_fsm_check 0 1 0.00
pwrmgr_sec_cm 0.840s 29.573us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
pwrmgr_tl_intg_err 0.680s 14.985us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.700s 925.403us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 1 1 100.00
pwrmgr_wakeup_reset 0.990s 234.058us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.740s 64.992us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.750s 29.189us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 0 1 0.00
pwrmgr_sec_cm 0.840s 29.573us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
pwrmgr_sec_cm 0.840s 29.573us 0 1 0.00
sec_cm_fsm_terminal 0 1 0.00
pwrmgr_sec_cm 0.840s 29.573us 0 1 0.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.690s 53.609us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.750s 48.924us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.970s 284.632us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.810s 20.739us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.810s 20.739us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 0.920s 403.428us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 10.050s 3875.880us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
pwrmgr_reset 107697570252611643961798333716595578450840916231044412316360010062284443068293 146
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((!clk_en) || status)'
pwrmgr_escalation_timeout 10580687969215007658397723778754742213553820189043224107691636254635408046729 79
UVM_ERROR @ 403428035 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 403428035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [pwrmgr_common_vseq] expect alert:fatal_fault to fire
pwrmgr_tl_intg_err 22586985863525746929344589584325700269517704466263512537454851402899189641212 78
UVM_INFO @ 14984901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_sec_cm 58379220186632759696912595864801069251603404023713983531509968478780216327081 85
UVM_INFO @ 29573271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---