Simulation Results: rom_ctrl/64kb

 
28/04/2026 15:30:29 DVSim: v1.32.0 sha: f8cd0a3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.74 %
  • code
  • 97.86 %
  • assert
  • 96.66 %
  • func
  • 95.70 %
  • line
  • 99.46 %
  • branch
  • 98.91 %
  • cond
  • 97.62 %
  • toggle
  • 100.00 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 7.480s 1536.233us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 7.570s 707.322us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 6.950s 294.162us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 6.230s 213.085us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 6.600s 986.191us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 7.110s 805.739us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 6.950s 294.162us 1 1 100.00
rom_ctrl_csr_aliasing 6.600s 986.191us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 10.850s 19547.572us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 5.530s 377.224us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 8.800s 301.130us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 19.560s 3098.834us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 14.120s 919.447us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 7.270s 304.152us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 10.350s 1027.888us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 10.350s 1027.888us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 7.570s 707.322us 1 1 100.00
rom_ctrl_csr_rw 6.950s 294.162us 1 1 100.00
rom_ctrl_csr_aliasing 6.600s 986.191us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.530s 300.191us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 7.570s 707.322us 1 1 100.00
rom_ctrl_csr_rw 6.950s 294.162us 1 1 100.00
rom_ctrl_csr_aliasing 6.600s 986.191us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.530s 300.191us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 106.810s 6018.519us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 34.140s 20708.217us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 226.590s 726.071us 1 1 100.00
rom_ctrl_tl_intg_err 95.100s 381.410us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 226.590s 726.071us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 226.590s 726.071us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 106.810s 6018.519us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 106.810s 6018.519us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 106.810s 6018.519us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 106.810s 6018.519us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 106.810s 6018.519us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 226.590s 726.071us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 226.590s 726.071us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 7.480s 1536.233us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 7.480s 1536.233us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 7.480s 1536.233us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 95.100s 381.410us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 106.810s 6018.519us 1 1 100.00
rom_ctrl_kmac_err_chk 14.120s 919.447us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 106.810s 6018.519us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 106.810s 6018.519us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 106.810s 6018.519us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 34.140s 20708.217us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 226.590s 726.071us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 57.770s 2235.332us 1 1 100.00