Simulation Results: rstmgr

 
28/04/2026 15:30:29 DVSim: v1.32.0 sha: f8cd0a3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.25 %
  • code
  • 99.37 %
  • assert
  • 97.86 %
  • func
  • 94.53 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.82 %
  • toggle
  • 99.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.090s 123.161us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.860s 144.444us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 1.000s 68.860us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 6.400s 2004.204us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.140s 103.858us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 0.980s 144.402us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 1.000s 68.860us 1 1 100.00
rstmgr_csr_aliasing 1.140s 103.858us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.920s 120.785us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.780s 339.331us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.800s 79.612us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.850s 1668.796us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.850s 1668.796us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.850s 1668.796us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.850s 1668.796us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 4.180s 1671.042us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.870s 70.572us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.950s 492.411us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.950s 492.411us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.860s 144.444us 1 1 100.00
rstmgr_csr_rw 1.000s 68.860us 1 1 100.00
rstmgr_csr_aliasing 1.140s 103.858us 1 1 100.00
rstmgr_same_csr_outstanding 1.340s 212.458us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.860s 144.444us 1 1 100.00
rstmgr_csr_rw 1.000s 68.860us 1 1 100.00
rstmgr_csr_aliasing 1.140s 103.858us 1 1 100.00
rstmgr_same_csr_outstanding 1.340s 212.458us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 10.040s 8532.757us 1 1 100.00
rstmgr_tl_intg_err 2.670s 937.584us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 10.040s 8532.757us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 10.040s 8532.757us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.670s 937.584us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.020s 146.027us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 6.270s 2447.753us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.090s 302.204us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 10.040s 8532.757us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 1.000s 68.860us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 1.000s 68.860us 1 1 100.00