Simulation Results: rv_timer

 
28/04/2026 15:30:29 DVSim: v1.32.0 sha: f8cd0a3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.69 %
  • code
  • 100.00 %
  • assert
  • 96.82 %
  • func
  • 93.24 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.630s 71.218us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.580s 36.316us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.570s 23.192us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.480s 88.729us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.950s 37.382us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.350s 70.369us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.570s 23.192us 1 1 100.00
rv_timer_csr_aliasing 0.950s 37.382us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.720s 183.341us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 1.520s 842.036us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 527.370s 457586.699us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 527.370s 457586.699us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 2.900s 4232.894us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.590s 63.948us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.560s 38.683us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.660s 427.399us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.660s 427.399us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.580s 36.316us 1 1 100.00
rv_timer_csr_rw 0.570s 23.192us 1 1 100.00
rv_timer_csr_aliasing 0.950s 37.382us 1 1 100.00
rv_timer_same_csr_outstanding 0.730s 37.114us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.580s 36.316us 1 1 100.00
rv_timer_csr_rw 0.570s 23.192us 1 1 100.00
rv_timer_csr_aliasing 0.950s 37.382us 1 1 100.00
rv_timer_same_csr_outstanding 0.730s 37.114us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.840s 94.282us 1 1 100.00
rv_timer_tl_intg_err 0.950s 433.117us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 0.950s 433.117us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 1 1 100.00
rv_timer_min 0.610s 24.884us 1 1 100.00
max_value 0 1 0.00
rv_timer_max 0.730s 178.539us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 19.530s 11404.667us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*])
rv_timer_max 8032447112444455213048910759216552921469790120203666456106052509504732418578 75
UVM_INFO @ 178539075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == *
rv_timer_random_reset 64256660896959393312091439823858191090846777525819705496806622610672933533388 76
UVM_INFO @ 183340671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---