Simulation Results: spi_device/1r1w

 
28/04/2026 15:30:29 DVSim: v1.32.0 sha: f8cd0a3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.92 %
  • code
  • 93.29 %
  • assert
  • 94.64 %
  • func
  • 75.84 %
  • line
  • 99.09 %
  • branch
  • 98.35 %
  • cond
  • 96.29 %
  • toggle
  • 83.36 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
92.31%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 27.970s 6277.671us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.050s 29.901us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.150s 137.603us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 24.370s 541.932us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 16.800s 3628.562us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.080s 98.876us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.150s 137.603us 1 1 100.00
spi_device_csr_aliasing 16.800s 3628.562us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.980s 72.350us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.730s 110.211us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.750s 17.420us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.710s 4.300us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.670s 7.951us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.110s 145.697us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.110s 145.697us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 3.380s 6008.185us 1 1 100.00
spi_device_tpm_sts_read 0.920s 168.050us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 16.100s 13681.401us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 1.880s 59.502us 1 1 100.00
spi_device_flash_all 63.830s 29053.935us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.900s 1082.994us 1 1 100.00
spi_device_flash_all 63.830s 29053.935us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.900s 1082.994us 1 1 100.00
spi_device_flash_all 63.830s 29053.935us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 63.830s 29053.935us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 2.000s 117.568us 1 1 100.00
spi_device_flash_all 63.830s 29053.935us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 2.000s 117.568us 1 1 100.00
spi_device_flash_all 63.830s 29053.935us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 2.000s 117.568us 1 1 100.00
spi_device_flash_all 63.830s 29053.935us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 2.000s 117.568us 1 1 100.00
spi_device_flash_all 63.830s 29053.935us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 2.000s 117.568us 1 1 100.00
spi_device_flash_all 63.830s 29053.935us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 5.650s 531.635us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 5.370s 1260.241us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 5.370s 1260.241us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 5.370s 1260.241us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 6.400s 288.737us 1 1 100.00
spi_device_read_buffer_direct 2.510s 89.722us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 5.370s 1260.241us 1 1 100.00
spi_device_flash_all 63.830s 29053.935us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 63.830s 29053.935us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 63.830s 29053.935us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 3.160s 2302.547us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 3.160s 2302.547us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 27.970s 6277.671us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 162.670s 58028.467us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 199.280s 81817.422us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.830s 40.656us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.830s 42.064us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 2.540s 210.649us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 2.540s 210.649us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.050s 29.901us 1 1 100.00
spi_device_csr_rw 1.150s 137.603us 1 1 100.00
spi_device_csr_aliasing 16.800s 3628.562us 1 1 100.00
spi_device_same_csr_outstanding 1.480s 269.887us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.050s 29.901us 1 1 100.00
spi_device_csr_rw 1.150s 137.603us 1 1 100.00
spi_device_csr_aliasing 16.800s 3628.562us 1 1 100.00
spi_device_same_csr_outstanding 1.480s 269.887us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 0.970s 135.840us 1 1 100.00
spi_device_tl_intg_err 5.580s 208.287us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 5.580s 208.287us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 56.900s 3671.032us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*])
spi_device_mem_parity 78743519360259276283270739775169415434889657322810940843334069570876387458390 76
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 3633027 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 3633027 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[990])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*])
spi_device_ram_cfg 101850556509816871143678421065575170705736475560816795270493375668837477907258 76
UVM_ERROR @ 5675971 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x808c75 [100000001000110001110101] vs 0x0 [0])
UVM_ERROR @ 5730971 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xbc1f28 [101111000001111100101000] vs 0x0 [0])
UVM_ERROR @ 5758971 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe565df [111001010110010111011111] vs 0x0 [0])
UVM_ERROR @ 5832971 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x913168 [100100010011000101101000] vs 0x0 [0])