Simulation Results: spi_device/2p

 
28/04/2026 15:30:29 DVSim: v1.32.0 sha: f8cd0a3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.21 %
  • code
  • 94.18 %
  • assert
  • 94.62 %
  • func
  • 75.84 %
  • line
  • 99.16 %
  • branch
  • 98.47 %
  • cond
  • 96.17 %
  • toggle
  • 87.74 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 198.560s 32668.682us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.000s 34.527us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.400s 278.279us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 16.450s 1580.820us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 12.060s 778.142us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 1.530s 25.875us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.400s 278.279us 1 1 100.00
spi_device_csr_aliasing 12.060s 778.142us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.960s 27.301us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.410s 83.879us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.850s 31.280us 1 1 100.00
mem_parity 1 1 100.00
spi_device_mem_parity 0.900s 104.031us 1 1 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 0.950s 38.753us 1 1 100.00
tpm_read 1 1 100.00
spi_device_tpm_rw 0.680s 40.280us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 0.680s 40.280us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 3.350s 1200.960us 1 1 100.00
spi_device_tpm_sts_read 0.810s 137.189us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 8.360s 1255.250us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 2.190s 56.331us 1 1 100.00
spi_device_flash_all 0.910s 19.348us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 4.790s 5783.350us 1 1 100.00
spi_device_flash_all 0.910s 19.348us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 4.790s 5783.350us 1 1 100.00
spi_device_flash_all 0.910s 19.348us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 0.910s 19.348us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 2.120s 289.970us 1 1 100.00
spi_device_flash_all 0.910s 19.348us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 2.120s 289.970us 1 1 100.00
spi_device_flash_all 0.910s 19.348us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 2.120s 289.970us 1 1 100.00
spi_device_flash_all 0.910s 19.348us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 2.120s 289.970us 1 1 100.00
spi_device_flash_all 0.910s 19.348us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 2.120s 289.970us 1 1 100.00
spi_device_flash_all 0.910s 19.348us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 6.130s 1810.192us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 1.780s 136.404us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 1.780s 136.404us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 1.780s 136.404us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 2.610s 1197.828us 1 1 100.00
spi_device_read_buffer_direct 4.070s 1727.356us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 1.780s 136.404us 1 1 100.00
spi_device_flash_all 0.910s 19.348us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 0.910s 19.348us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 0.910s 19.348us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 7.320s 735.288us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 7.320s 735.288us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 198.560s 32668.682us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 216.360s 206318.107us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 110.070s 10462.452us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.720s 67.235us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.680s 40.761us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 2.610s 420.802us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 2.610s 420.802us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.000s 34.527us 1 1 100.00
spi_device_csr_rw 1.400s 278.279us 1 1 100.00
spi_device_csr_aliasing 12.060s 778.142us 1 1 100.00
spi_device_same_csr_outstanding 2.960s 147.573us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.000s 34.527us 1 1 100.00
spi_device_csr_rw 1.400s 278.279us 1 1 100.00
spi_device_csr_aliasing 12.060s 778.142us 1 1 100.00
spi_device_same_csr_outstanding 2.960s 147.573us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.030s 40.241us 1 1 100.00
spi_device_tl_intg_err 5.780s 220.506us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 5.780s 220.506us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 31.680s 17284.421us 1 1 100.00