Simulation Results: spi_host

 
28/04/2026 15:30:29 DVSim: v1.32.0 sha: f8cd0a3 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.68 %
  • code
  • 95.03 %
  • assert
  • 93.94 %
  • func
  • 89.08 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 2.000s 74.537us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 2.000s 19.574us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 2.000s 155.157us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 3.000s 58.504us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 19.366us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 1.000s 63.200us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 2.000s 155.157us 1 1 100.00
spi_host_csr_aliasing 1.000s 19.366us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 17.400us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 23.544us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 1.000s 132.313us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 7.000s 433.468us 1 1 100.00
spi_host_error_cmd 1.000s 17.818us 1 1 100.00
spi_host_event 9.000s 1898.622us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 1.000s 78.144us 1 1 100.00
speed 1 1 100.00
spi_host_speed 1.000s 78.144us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 1.000s 78.144us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 55.000s 3569.983us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 2.000s 38.933us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 1.000s 78.144us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 1.000s 78.144us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 2.000s 74.537us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 2.000s 74.537us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 10.000s 1242.347us 1 1 100.00
spien 1 1 100.00
spi_host_spien 6.000s 524.928us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 63.000s 6275.883us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 14.000s 3310.075us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 7.000s 433.468us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 30.007us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 22.151us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 3.000s 360.200us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 3.000s 360.200us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 2.000s 19.574us 1 1 100.00
spi_host_csr_rw 2.000s 155.157us 1 1 100.00
spi_host_csr_aliasing 1.000s 19.366us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 219.614us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 2.000s 19.574us 1 1 100.00
spi_host_csr_rw 2.000s 155.157us 1 1 100.00
spi_host_csr_aliasing 1.000s 19.366us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 219.614us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 1.000s 431.732us 1 1 100.00
spi_host_sec_cm 2.000s 262.105us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 1.000s 431.732us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_host_upper_range_clkdiv 138.000s 16968.504us 1 1 100.00