Simulation Results: sram_ctrl/main

 
28/04/2026 15:30:29 DVSim: v1.32.0 sha: f8cd0a3 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.01 %
  • code
  • 96.76 %
  • assert
  • 96.46 %
  • func
  • 91.80 %
  • block
  • 96.15 %
  • line
  • 96.88 %
  • branch
  • 94.33 %
  • toggle
  • 95.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 3.000s 1418.305us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 41.720us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 13.600us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 365.751us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 51.486us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 1396.777us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 13.600us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 51.486us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 110.000s 9143.768us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 100.000s 5610.207us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 18.000s 8019.929us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 171.000s 19344.911us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 151.000s 56374.533us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 34.000s 29007.448us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 38.000s 10768.738us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 21.000s 18410.457us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 5.000s 2899.533us 1 1 100.00
sram_ctrl_partial_access_b2b 85.000s 14274.866us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 5.000s 697.694us 1 1 100.00
sram_ctrl_throughput_w_partial_write 4.000s 1392.886us 1 1 100.00
sram_ctrl_throughput_w_readback 4.000s 827.473us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 11.000s 5548.058us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.000s 697.205us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 96.000s 47083.741us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 20.154us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 57.209us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 57.209us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 41.720us 1 1 100.00
sram_ctrl_csr_rw 1.000s 13.600us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 51.486us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 15.366us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 41.720us 1 1 100.00
sram_ctrl_csr_rw 1.000s 13.600us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 51.486us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 15.366us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 17.000s 33513.749us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 426.797us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 306.435us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 426.797us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 306.435us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 11.000s 5548.058us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 11.000s 5548.058us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 13.600us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 21.000s 18410.457us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 21.000s 18410.457us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 21.000s 18410.457us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 38.000s 10768.738us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.000s 2581.337us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 17.000s 33513.749us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 4.000s 1397.206us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 1418.305us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 1418.305us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 21.000s 18410.457us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 426.797us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 38.000s 10768.738us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 426.797us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 426.797us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 3.000s 1418.305us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 426.797us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 7.000s 302.119us 1 1 100.00