Simulation Results: sysrst_ctrl

 
28/04/2026 15:30:29 DVSim: v1.32.0 sha: f8cd0a3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.87 %
  • code
  • 91.88 %
  • assert
  • 91.86 %
  • func
  • 61.88 %
  • line
  • 96.84 %
  • branch
  • 96.92 %
  • cond
  • 93.85 %
  • toggle
  • 100.00 %
  • FSM
  • 71.79 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 3.090s 2118.218us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 5.340s 2468.730us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 1.010s 2484.033us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 1.450s 2563.007us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 6.580s 6024.283us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 5.070s 2053.994us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 22.790s 39036.413us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 8.580s 3144.976us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 1.440s 2331.159us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 5.070s 2053.994us 1 1 100.00
sysrst_ctrl_csr_aliasing 8.580s 3144.976us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 240.610s 126421.763us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 55.330s 26332.055us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 6.910s 3118.355us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 6.200s 3074.445us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 1.010s 2687.424us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 5.630s 2018.767us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 3.110s 4788.385us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 1.590s 2646.482us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 2.790s 8541.316us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 73.290s 41449.571us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 24.730s 12750.117us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 2.320s 2041.795us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 4.550s 2017.682us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 2.720s 2041.038us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 2.720s 2041.038us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 6.580s 6024.283us 1 1 100.00
sysrst_ctrl_csr_rw 5.070s 2053.994us 1 1 100.00
sysrst_ctrl_csr_aliasing 8.580s 3144.976us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 13.380s 4649.560us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 6.580s 6024.283us 1 1 100.00
sysrst_ctrl_csr_rw 5.070s 2053.994us 1 1 100.00
sysrst_ctrl_csr_aliasing 8.580s 3144.976us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 13.380s 4649.560us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 13.220s 22095.302us 1 1 100.00
sysrst_ctrl_tl_intg_err 23.380s 22301.779us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 23.380s 22301.779us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 4.260s 6815.531us 1 1 100.00