Simulation Results: uart

 
28/04/2026 15:30:29 DVSim: v1.32.0 sha: f8cd0a3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.09 %
  • code
  • 95.70 %
  • assert
  • 97.12 %
  • func
  • 59.46 %
  • line
  • 99.06 %
  • branch
  • 96.97 %
  • cond
  • 95.22 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.390s 541.408us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.680s 14.946us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.680s 87.469us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.930s 758.698us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.710s 185.883us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.780s 19.694us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.680s 87.469us 1 1 100.00
uart_csr_aliasing 0.710s 185.883us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 16.550s 37717.207us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.390s 541.408us 1 1 100.00
uart_tx_rx 16.550s 37717.207us 1 1 100.00
parity_error 2 2 100.00
uart_intr 31.540s 23604.702us 1 1 100.00
uart_rx_parity_err 39.720s 76055.759us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 16.550s 37717.207us 1 1 100.00
uart_intr 31.540s 23604.702us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 30.530s 66022.831us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 68.660s 483044.282us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 22.990s 65513.066us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 31.540s 23604.702us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 31.540s 23604.702us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 31.540s 23604.702us 1 1 100.00
perf 1 1 100.00
uart_perf 163.810s 11101.867us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 0.680s 793.280us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 0.680s 793.280us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 34.320s 27070.987us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 7.430s 5856.255us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 2.250s 1178.194us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 4.740s 1380.012us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 519.680s 191184.407us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 57.230s 150000.915us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.630s 13.430us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.710s 45.130us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.450s 338.824us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.450s 338.824us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.680s 14.946us 1 1 100.00
uart_csr_rw 0.680s 87.469us 1 1 100.00
uart_csr_aliasing 0.710s 185.883us 1 1 100.00
uart_same_csr_outstanding 1.030s 18.476us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.680s 14.946us 1 1 100.00
uart_csr_rw 0.680s 87.469us 1 1 100.00
uart_csr_aliasing 0.710s 185.883us 1 1 100.00
uart_same_csr_outstanding 1.030s 18.476us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.180s 120.807us 1 1 100.00
uart_tl_intg_err 1.440s 374.563us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.440s 374.563us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 32.790s 13758.544us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: *
uart_noise_filter 112968423152477612697575743026731575717898752634405083797261350094979966062080 80
UVM_ERROR @ 26776603640 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 26776655185 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (224 [0xe0] vs 251 [0xfb]) reg name: uart_reg_block.rdata
UVM_ERROR @ 26796623718 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 26796623718 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0