Simulation Results: adc_ctrl

 
29/04/2026 15:30:23 DVSim: v1.33.0 sha: a64a82b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 65.90 %
  • code
  • 93.42 %
  • assert
  • 91.41 %
  • func
  • 12.87 %
  • line
  • 98.86 %
  • branch
  • 97.40 %
  • cond
  • 87.30 %
  • toggle
  • 99.76 %
  • FSM
  • 83.78 %
Validation stages
V1
100.00%
V2
52.63%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 3.910s 5951.995us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 2.620s 1269.698us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.550s 542.711us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 29.360s 53081.631us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 3.190s 853.841us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 2.160s 436.519us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.550s 542.711us 1 1 100.00
adc_ctrl_csr_aliasing 3.190s 853.841us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 0 1 0.00
adc_ctrl_filters_polled 1.340s 459.441us 0 1 0.00
filters_polled_fixed 0 1 0.00
adc_ctrl_filters_polled_fixed 0.870s 502.142us 0 1 0.00
filters_interrupt 0 1 0.00
adc_ctrl_filters_interrupt 0.980s 445.049us 0 1 0.00
filters_interrupt_fixed 0 1 0.00
adc_ctrl_filters_interrupt_fixed 0.660s 458.263us 0 1 0.00
filters_wakeup 0 1 0.00
adc_ctrl_filters_wakeup 1.100s 285.098us 0 1 0.00
filters_wakeup_fixed 0 1 0.00
adc_ctrl_filters_wakeup_fixed 0.820s 303.525us 0 1 0.00
filters_both 0 1 0.00
adc_ctrl_filters_both 1.080s 389.120us 0 1 0.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 0.790s 348.782us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 5.800s 2788.678us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 42.780s 28136.444us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 109.960s 64466.257us 1 1 100.00
stress_all 0 1 0.00
adc_ctrl_stress_all 2.060s 1931.635us 0 1 0.00
alert_test 1 1 100.00
adc_ctrl_alert_test 1.770s 475.111us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 0.630s 361.417us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 2.250s 825.044us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 2.250s 825.044us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 2.620s 1269.698us 1 1 100.00
adc_ctrl_csr_rw 1.550s 542.711us 1 1 100.00
adc_ctrl_csr_aliasing 3.190s 853.841us 1 1 100.00
adc_ctrl_same_csr_outstanding 1.510s 2366.845us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 2.620s 1269.698us 1 1 100.00
adc_ctrl_csr_rw 1.550s 542.711us 1 1 100.00
adc_ctrl_csr_aliasing 3.190s 853.841us 1 1 100.00
adc_ctrl_same_csr_outstanding 1.510s 2366.845us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 2.230s 7979.555us 1 1 100.00
adc_ctrl_tl_intg_err 9.840s 8517.438us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 9.840s 8517.438us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
adc_ctrl_stress_all_with_rand_reset 1.540s 1133.613us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [*, *]
adc_ctrl_filters_polled 53786988027219640393248682006663136188751401146602285719352229493537014076631 389
UVM_INFO @ 459440869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 78992566440715880718000645857756520399563637564363810231633846387110010108012 389
UVM_INFO @ 502141754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 81222686237516024057546974341979517270282549268387338070744893648631705536422 389
UVM_INFO @ 445048857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 98868854097897301884965374670282834085154756231213833851974433706987802776097 389
UVM_INFO @ 458263386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 23601167762175689795762731159682855952116342222096560134909771067617156866155 389
UVM_INFO @ 285097858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 102834973945538283352608281263731270208361435755352192401718959736795961357360 389
UVM_INFO @ 303525350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 53788776413391242642030837373122548610764538207993411319746022051804200317011 389
UVM_INFO @ 348781943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 107405866733398220625751407344059331452942662588029437202047324275837484583939 389
UVM_INFO @ 389119783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 30812166125519844086156009252255556029050829468624761592378895105158051104052 409
UVM_INFO @ 1133613081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 108277955356138697146882718540142931284539434906529322835288268850395999671023 423
UVM_INFO @ 1931635221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---