Simulation Results: aes/masked

 
29/04/2026 15:30:23 DVSim: v1.33.0 sha: a64a82b json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.58 %
  • code
  • 95.72 %
  • assert
  • 98.29 %
  • func
  • 65.74 %
  • block
  • 95.88 %
  • line
  • 97.56 %
  • branch
  • 89.84 %
  • toggle
  • 98.05 %
  • FSM
  • 97.42 %
Validation stages
V1
100.00%
V2
94.74%
V2S
88.89%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 68.652us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 66.804us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 203.644us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 53.296us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 7.000s 801.128us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 288.205us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 97.703us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 53.296us 1 1 100.00
aes_csr_aliasing 3.000s 288.205us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 66.804us 1 1 100.00
aes_config_error 2.000s 91.353us 1 1 100.00
aes_stress 3.000s 103.936us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 66.804us 1 1 100.00
aes_config_error 2.000s 91.353us 1 1 100.00
aes_stress 3.000s 103.936us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 103.936us 1 1 100.00
aes_b2b 19.000s 334.717us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 103.936us 1 1 100.00
multi_message 3 4 75.00
aes_smoke 3.000s 66.804us 1 1 100.00
aes_config_error 2.000s 91.353us 1 1 100.00
aes_stress 3.000s 103.936us 1 1 100.00
aes_alert_reset 50.000s 10011.325us 0 1 0.00
failure_test 2 3 66.67
aes_man_cfg_err 2.000s 73.952us 1 1 100.00
aes_config_error 2.000s 91.353us 1 1 100.00
aes_alert_reset 50.000s 10011.325us 0 1 0.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 265.005us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 11.000s 2497.395us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 7.000s 1021.408us 1 1 100.00
reset_recovery 0 1 0.00
aes_alert_reset 50.000s 10011.325us 0 1 0.00
stress 1 1 100.00
aes_stress 3.000s 103.936us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 103.936us 1 1 100.00
aes_sideload 8.000s 83.840us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 4.000s 878.635us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 8.000s 197.623us 1 1 100.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 3.000s 138.014us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 93.367us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 174.294us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 174.294us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 203.644us 1 1 100.00
aes_csr_rw 2.000s 53.296us 1 1 100.00
aes_csr_aliasing 3.000s 288.205us 1 1 100.00
aes_same_csr_outstanding 2.000s 103.360us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 203.644us 1 1 100.00
aes_csr_rw 2.000s 53.296us 1 1 100.00
aes_csr_aliasing 3.000s 288.205us 1 1 100.00
aes_same_csr_outstanding 2.000s 103.360us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 11.000s 488.162us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 20.000s 10049.016us 0 1 0.00
aes_control_fi 3.000s 61.568us 1 1 100.00
aes_cipher_fi 2.000s 87.994us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 148.722us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 148.722us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 148.722us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 148.722us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 4.000s 891.118us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 669.821us 1 1 100.00
aes_tl_intg_err 3.000s 501.299us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 501.299us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
aes_alert_reset 50.000s 10011.325us 0 1 0.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 148.722us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 148.722us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 3.000s 66.804us 1 1 100.00
aes_stress 3.000s 103.936us 1 1 100.00
aes_alert_reset 50.000s 10011.325us 0 1 0.00
aes_core_fi 2.000s 85.384us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 3.000s 138.014us 1 1 100.00
aes_config_error 2.000s 91.353us 1 1 100.00
aes_stress 3.000s 103.936us 1 1 100.00
aes_core_fi 2.000s 85.384us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 148.722us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 108.841us 1 1 100.00
aes_stress 3.000s 103.936us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 103.936us 1 1 100.00
aes_sideload 8.000s 83.840us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 108.841us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 108.841us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 108.841us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 108.841us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 108.841us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 103.936us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 103.936us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 20.000s 10049.016us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 20.000s 10049.016us 0 1 0.00
aes_control_fi 3.000s 61.568us 1 1 100.00
aes_cipher_fi 2.000s 87.994us 1 1 100.00
aes_ctr_fi 3.000s 97.650us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 20.000s 10049.016us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 20.000s 10049.016us 0 1 0.00
aes_control_fi 3.000s 61.568us 1 1 100.00
aes_cipher_fi 2.000s 87.994us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 87.994us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 20.000s 10049.016us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 20.000s 10049.016us 0 1 0.00
aes_control_fi 3.000s 61.568us 1 1 100.00
aes_ctr_fi 3.000s 97.650us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 20.000s 10049.016us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 20.000s 10049.016us 0 1 0.00
aes_control_fi 3.000s 61.568us 1 1 100.00
aes_cipher_fi 2.000s 87.994us 1 1 100.00
aes_ctr_fi 3.000s 97.650us 1 1 100.00
sec_cm_main_fsm_global_esc 0 1 0.00
aes_alert_reset 50.000s 10011.325us 0 1 0.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 20.000s 10049.016us 0 1 0.00
aes_control_fi 3.000s 61.568us 1 1 100.00
aes_cipher_fi 2.000s 87.994us 1 1 100.00
aes_ctr_fi 3.000s 97.650us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 20.000s 10049.016us 0 1 0.00
aes_control_fi 3.000s 61.568us 1 1 100.00
aes_cipher_fi 2.000s 87.994us 1 1 100.00
aes_ctr_fi 3.000s 97.650us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 20.000s 10049.016us 0 1 0.00
aes_control_fi 3.000s 61.568us 1 1 100.00
aes_ctr_fi 3.000s 97.650us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_fi 20.000s 10049.016us 0 1 0.00
aes_ghash_fi 1.000s 61.338us 1 1 100.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 20.000s 10049.016us 0 1 0.00
aes_control_fi 3.000s 61.568us 1 1 100.00
aes_cipher_fi 2.000s 87.994us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
aes_stress_all_with_rand_reset 40.000s 1773.924us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:454) [aes_alert_reset_vseq] wait timeout occurred!
aes_alert_reset 200913763680806850998980708048966142093898815825148456181275682907107012590 2157
UVM_INFO @ 10011325047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [aes_fi_vseq] wait timeout occurred!
aes_fi 57955064091321649633087072849576264991535039299281214532371275391258226612364 4448
UVM_INFO @ 10049015701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---