Simulation Results: aes/unmasked

 
29/04/2026 15:30:23 DVSim: v1.33.0 sha: a64a82b json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 84.46 %
  • code
  • 90.84 %
  • assert
  • 97.75 %
  • func
  • 64.80 %
  • block
  • 90.96 %
  • line
  • 93.35 %
  • branch
  • 83.37 %
  • toggle
  • 97.99 %
  • FSM
  • 88.65 %
Validation stages
V1
100.00%
V2
89.47%
V2S
88.89%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 65.105us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 108.401us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 58.319us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 159.296us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 3.000s 443.977us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 120.952us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 61.404us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 159.296us 1 1 100.00
aes_csr_aliasing 3.000s 120.952us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 108.401us 1 1 100.00
aes_config_error 2.000s 165.534us 1 1 100.00
aes_stress 3.000s 138.380us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 108.401us 1 1 100.00
aes_config_error 2.000s 165.534us 1 1 100.00
aes_stress 3.000s 138.380us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 138.380us 1 1 100.00
aes_b2b 3.000s 78.445us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 138.380us 1 1 100.00
multi_message 3 4 75.00
aes_smoke 2.000s 108.401us 1 1 100.00
aes_config_error 2.000s 165.534us 1 1 100.00
aes_stress 3.000s 138.380us 1 1 100.00
aes_alert_reset 16.000s 10019.510us 0 1 0.00
failure_test 2 3 66.67
aes_man_cfg_err 2.000s 108.469us 1 1 100.00
aes_config_error 2.000s 165.534us 1 1 100.00
aes_alert_reset 16.000s 10019.510us 0 1 0.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 75.320us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 825.904us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 3.000s 237.920us 1 1 100.00
reset_recovery 0 1 0.00
aes_alert_reset 16.000s 10019.510us 0 1 0.00
stress 1 1 100.00
aes_stress 3.000s 138.380us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 138.380us 1 1 100.00
aes_sideload 3.000s 808.793us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 67.414us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 37.000s 10199.533us 0 1 0.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 2.000s 213.208us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 68.575us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 75.884us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 75.884us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 58.319us 1 1 100.00
aes_csr_rw 1.000s 159.296us 1 1 100.00
aes_csr_aliasing 3.000s 120.952us 1 1 100.00
aes_same_csr_outstanding 2.000s 94.028us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 58.319us 1 1 100.00
aes_csr_rw 1.000s 159.296us 1 1 100.00
aes_csr_aliasing 3.000s 120.952us 1 1 100.00
aes_same_csr_outstanding 2.000s 94.028us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 2.000s 65.761us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 28.000s 10007.522us 0 1 0.00
aes_control_fi 2.000s 49.312us 1 1 100.00
aes_cipher_fi 1.000s 200.300us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 1.000s 61.867us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 1.000s 61.867us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 1.000s 61.867us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 1.000s 61.867us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 576.047us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 9.000s 2603.206us 1 1 100.00
aes_tl_intg_err 3.000s 309.710us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 309.710us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
aes_alert_reset 16.000s 10019.510us 0 1 0.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 61.867us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 61.867us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 2.000s 108.401us 1 1 100.00
aes_stress 3.000s 138.380us 1 1 100.00
aes_alert_reset 16.000s 10019.510us 0 1 0.00
aes_core_fi 2.000s 80.432us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 2.000s 213.208us 1 1 100.00
aes_config_error 2.000s 165.534us 1 1 100.00
aes_stress 3.000s 138.380us 1 1 100.00
aes_core_fi 2.000s 80.432us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 61.867us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 84.284us 1 1 100.00
aes_stress 3.000s 138.380us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 138.380us 1 1 100.00
aes_sideload 3.000s 808.793us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 84.284us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 84.284us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 84.284us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 84.284us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 84.284us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 138.380us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 138.380us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 28.000s 10007.522us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 28.000s 10007.522us 0 1 0.00
aes_control_fi 2.000s 49.312us 1 1 100.00
aes_cipher_fi 1.000s 200.300us 1 1 100.00
aes_ctr_fi 2.000s 120.069us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 28.000s 10007.522us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 28.000s 10007.522us 0 1 0.00
aes_control_fi 2.000s 49.312us 1 1 100.00
aes_cipher_fi 1.000s 200.300us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 1.000s 200.300us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 28.000s 10007.522us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 28.000s 10007.522us 0 1 0.00
aes_control_fi 2.000s 49.312us 1 1 100.00
aes_ctr_fi 2.000s 120.069us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 28.000s 10007.522us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 28.000s 10007.522us 0 1 0.00
aes_control_fi 2.000s 49.312us 1 1 100.00
aes_cipher_fi 1.000s 200.300us 1 1 100.00
aes_ctr_fi 2.000s 120.069us 1 1 100.00
sec_cm_main_fsm_global_esc 0 1 0.00
aes_alert_reset 16.000s 10019.510us 0 1 0.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 28.000s 10007.522us 0 1 0.00
aes_control_fi 2.000s 49.312us 1 1 100.00
aes_cipher_fi 1.000s 200.300us 1 1 100.00
aes_ctr_fi 2.000s 120.069us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 28.000s 10007.522us 0 1 0.00
aes_control_fi 2.000s 49.312us 1 1 100.00
aes_cipher_fi 1.000s 200.300us 1 1 100.00
aes_ctr_fi 2.000s 120.069us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 28.000s 10007.522us 0 1 0.00
aes_control_fi 2.000s 49.312us 1 1 100.00
aes_ctr_fi 2.000s 120.069us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_fi 28.000s 10007.522us 0 1 0.00
aes_ghash_fi 1.000s 57.990us 1 1 100.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 28.000s 10007.522us 0 1 0.00
aes_control_fi 2.000s 49.312us 1 1 100.00
aes_cipher_fi 1.000s 200.300us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 26.000s 2712.802us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:454) [aes_alert_reset_vseq] wait timeout occurred!
aes_alert_reset 12124252015269017224834954486829769263671905998600952692862347497628482458980 2814
UVM_INFO @ 10019510197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 99213151005252629420968174489462339986335166060970377121379836197337756835434 37262
UVM_INFO @ 10199533376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [aes_fi_vseq] wait timeout occurred!
aes_fi 104012110277424197652654228424136036571150802066910247737475959952376242554717 2277
UVM_INFO @ 10007521828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
aes_stress_all_with_rand_reset 103645916841685938695142492201272588482812580241663135392409595649822004632298 2337
UVM_INFO @ 2712802071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---