Simulation Results: alert_handler

 
29/04/2026 15:30:23 DVSim: v1.33.0 sha: a64a82b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.68 %
  • code
  • 93.85 %
  • assert
  • 98.33 %
  • func
  • 79.85 %
  • line
  • 99.75 %
  • branch
  • 98.80 %
  • cond
  • 93.17 %
  • toggle
  • 93.64 %
  • FSM
  • 83.87 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 39.560s 2230.979us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 4.120s 197.615us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 4.050s 34.234us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 74.790s 1637.117us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 68.990s 1631.361us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 5.750s 185.357us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 4.050s 34.234us 1 1 100.00
alert_handler_csr_aliasing 68.990s 1631.361us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 72.360s 6620.340us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 30.180s 867.156us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 750.760s 37582.911us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 9.570s 218.596us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 39.560s 2230.979us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 23.100s 630.733us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 15.680s 825.507us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 212.970s 8898.673us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 874.970s 100101.514us 1 1 100.00
alert_handler_lpg_stub_clk 1814.700s 50685.570us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 1247.720s 121291.103us 1 1 100.00
alert_handler_entropy_stress_test 1 1 100.00
alert_handler_entropy_stress 26.630s 3900.480us 1 1 100.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 2.010s 17.860us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.260s 23.937us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 4.800s 60.648us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 4.800s 60.648us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 4.120s 197.615us 1 1 100.00
alert_handler_csr_rw 4.050s 34.234us 1 1 100.00
alert_handler_csr_aliasing 68.990s 1631.361us 1 1 100.00
alert_handler_same_csr_outstanding 13.700s 315.406us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 4.120s 197.615us 1 1 100.00
alert_handler_csr_rw 4.050s 34.234us 1 1 100.00
alert_handler_csr_aliasing 68.990s 1631.361us 1 1 100.00
alert_handler_same_csr_outstanding 13.700s 315.406us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 200.590s 23529.288us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 200.590s 23529.288us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 200.590s 23529.288us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 200.590s 23529.288us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 612.810s 13172.604us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 15.630s 2036.996us 1 1 100.00
alert_handler_tl_intg_err 2.910s 78.153us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 2.910s 78.153us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 200.590s 23529.288us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 39.560s 2230.979us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 39.560s 2230.979us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 39.560s 2230.979us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 39.560s 2230.979us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 9.570s 218.596us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 874.970s 100101.514us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 9.570s 218.596us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 750.760s 37582.911us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 750.760s 37582.911us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 15.630s 2036.996us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 15.630s 2036.996us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 15.630s 2036.996us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 15.630s 2036.996us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 15.630s 2036.996us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 15.630s 2036.996us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 15.630s 2036.996us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 15.630s 2036.996us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 15.630s 2036.996us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
alert_handler_stress_all_with_rand_reset 204.570s 6872.306us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state
alert_handler_ping_timeout 11479055061365400706611106266751031744926364415611158644263065474745554726537 138
UVM_INFO @ 8898673338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---