Simulation Results: chip

 
29/04/2026 15:30:23 DVSim: v1.33.0 sha: a64a82b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 71.52 %
  • code
  • 84.51 %
  • assert
  • 97.37 %
  • func
  • 32.69 %
  • line
  • 93.95 %
  • branch
  • 92.28 %
  • cond
  • 87.85 %
  • toggle
  • 91.35 %
  • FSM
  • 57.14 %
Validation stages
V1
94.44%
V2
78.06%
V2S
100.00%
V3
61.54%
unmapped
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 168.630s 2387.373us 1 1 100.00
chip_sw_example_rom 76.400s 2640.792us 1 1 100.00
chip_sw_example_manufacturer 144.580s 2960.263us 1 1 100.00
chip_sw_example_concurrency 157.190s 3542.891us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 219.840s 7713.623us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 509.770s 6039.655us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 273.890s 4058.823us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 3385.960s 30705.051us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
chip_csr_mem_rw_with_rand_reset 43.700s 1849.130us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 3385.960s 30705.051us 1 1 100.00
chip_csr_rw 509.770s 6039.655us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 7.000s 221.156us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 291.040s 4918.948us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 291.040s 4918.948us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 291.040s 4918.948us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 350.640s 4516.578us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 350.640s 4516.578us 1 1 100.00
chip_sw_uart_tx_rx_idx1 388.650s 4391.235us 1 1 100.00
chip_sw_uart_tx_rx_idx2 406.200s 5069.419us 1 1 100.00
chip_sw_uart_tx_rx_idx3 346.860s 4573.231us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 333.670s 3760.951us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 1117.840s 8232.562us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 332.750s 5297.718us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 202.880s 4878.430us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 202.880s 4878.430us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 0 1 0.00
chip_sw_sleep_pin_mio_dio_val 184.930s 3225.034us 0 1 0.00
chip_sw_sleep_pin_wake 1 1 100.00
chip_sw_sleep_pin_wake 149.660s 2539.729us 1 1 100.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 180.640s 4145.191us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 81.770s 3010.514us 1 1 100.00
chip_tap_straps_testunlock0 128.900s 3331.492us 1 1 100.00
chip_tap_straps_rma 134.920s 3612.948us 1 1 100.00
chip_tap_straps_prod 711.780s 12163.720us 1 1 100.00
chip_sw_pattgen_ios 1 1 100.00
chip_sw_pattgen_ios 163.160s 3090.032us 1 1 100.00
chip_sw_sleep_pwm_pulses 1 1 100.00
chip_sw_sleep_pwm_pulses 755.350s 8990.148us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 354.860s 6265.774us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 354.860s 6265.774us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 582.220s 8463.327us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 685.740s 9738.826us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 355.690s 3871.943us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 624.790s 5651.621us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3821.530s 19154.208us 1 1 100.00
chip_sw_aes_enc_jitter_en 142.040s 2822.787us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 832.880s 7747.307us 1 1 100.00
chip_sw_hmac_enc_jitter_en 206.540s 3226.343us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 562.110s 6298.860us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 182.190s 3136.394us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 347.510s 5428.571us 1 1 100.00
chip_sw_clkmgr_jitter 127.970s 2658.694us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 178.890s 3326.563us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 2 2 100.00
chip_sw_sensor_ctrl_alert 342.400s 5268.202us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 252.370s 5616.175us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 171.960s 3251.768us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 252.370s 5616.175us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 156.420s 3010.147us 1 1 100.00
chip_sw_aes_smoketest 135.980s 3334.175us 1 1 100.00
chip_sw_aon_timer_smoketest 172.160s 3003.538us 1 1 100.00
chip_sw_clkmgr_smoketest 130.830s 3076.056us 1 1 100.00
chip_sw_csrng_smoketest 169.160s 2949.522us 1 1 100.00
chip_sw_entropy_src_smoketest 600.880s 4967.066us 1 1 100.00
chip_sw_gpio_smoketest 187.560s 2833.982us 1 1 100.00
chip_sw_hmac_smoketest 215.580s 3668.535us 1 1 100.00
chip_sw_kmac_smoketest 147.380s 3432.195us 1 1 100.00
chip_sw_otbn_smoketest 1266.990s 9737.671us 1 1 100.00
chip_sw_pwrmgr_smoketest 259.450s 6435.306us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 263.240s 5970.713us 1 1 100.00
chip_sw_rv_plic_smoketest 141.020s 3334.998us 1 1 100.00
chip_sw_rv_timer_smoketest 174.460s 3214.786us 1 1 100.00
chip_sw_rstmgr_smoketest 146.700s 3049.637us 1 1 100.00
chip_sw_sram_ctrl_smoketest 150.230s 2903.672us 1 1 100.00
chip_sw_uart_smoketest 197.370s 2779.530us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 180.880s 3366.040us 1 1 100.00
chip_sw_rom_functests 0 1 0.00
rom_keymgr_functest 375.510s 4304.420us 0 1 0.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 7906.800s 62686.747us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 2978.490s 15339.172us 1 1 100.00
chip_sw_rom_raw_unlock 0 1 0.00
rom_raw_unlock 116.002s 0.000us 0 1 0.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 224.320s 3887.020us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 160.980s 3527.821us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 7384.250s 54337.018us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 7489.730s 58279.140us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 61.050s 2622.625us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 61.050s 2622.625us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 3385.960s 30705.051us 1 1 100.00
chip_same_csr_outstanding 1240.100s 16076.661us 1 1 100.00
chip_csr_hw_reset 219.840s 7713.623us 1 1 100.00
chip_csr_rw 509.770s 6039.655us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 3385.960s 30705.051us 1 1 100.00
chip_same_csr_outstanding 1240.100s 16076.661us 1 1 100.00
chip_csr_hw_reset 219.840s 7713.623us 1 1 100.00
chip_csr_rw 509.770s 6039.655us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 22.000s 1007.171us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 4.890s 54.004us 1 1 100.00
xbar_smoke_large_delays 34.210s 5626.027us 1 1 100.00
xbar_smoke_slow_rsp 49.160s 5708.001us 1 1 100.00
xbar_random_zero_delays 17.710s 275.662us 1 1 100.00
xbar_random_large_delays 107.070s 18819.471us 1 1 100.00
xbar_random_slow_rsp 313.640s 38231.893us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 16.010s 514.786us 1 1 100.00
xbar_error_and_unmapped_addr 4.270s 42.803us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 29.990s 1417.282us 1 1 100.00
xbar_error_and_unmapped_addr 4.270s 42.803us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 38.120s 852.532us 1 1 100.00
xbar_access_same_device_slow_rsp 75.020s 8918.646us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 32.450s 1702.662us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 73.780s 1572.585us 1 1 100.00
xbar_stress_all_with_error 65.410s 1553.302us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 206.810s 621.378us 1 1 100.00
xbar_stress_all_with_reset_error 132.330s 708.246us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 2978.490s 15339.172us 1 1 100.00
rom_e2e_shutdown_output 1 1 100.00
rom_e2e_shutdown_output 2703.680s 24701.293us 1 1 100.00
rom_e2e_shutdown_exception_c 1 1 100.00
rom_e2e_shutdown_exception_c 3042.220s 17121.309us 1 1 100.00
rom_e2e_boot_policy_valid 0 15 0.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 67.365s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 199.767s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 82.292s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 200.142s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 58.039s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 134.261s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 61.935s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 78.645s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 61.594s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 113.298s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 131.050s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 66.564s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 75.193s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 122.381s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 175.109s 0.000us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 17.040s 10.300us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 16.710s 10.360us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 16.870s 10.200us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 17.610s 10.260us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 18.530s 10.280us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 20.900s 10.260us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 16.980s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 19.900s 10.380us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 17.100s 10.320us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 16.300s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 16.730s 10.360us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 16.330s 10.300us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 17.710s 10.400us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 18.060s 10.120us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 16.530s 10.260us 0 1 0.00
rom_e2e_asm_init 0 5 0.00
rom_e2e_asm_init_test_unlocked0 72.109s 0.000us 0 1 0.00
rom_e2e_asm_init_dev 102.822s 0.000us 0 1 0.00
rom_e2e_asm_init_prod 38.190s 0.000us 0 1 0.00
rom_e2e_asm_init_prod_end 24.628s 0.000us 0 1 0.00
rom_e2e_asm_init_rma 15.104s 0.000us 0 1 0.00
rom_e2e_keymgr_init 3 3 100.00
rom_e2e_keymgr_init_rom_ext_meas 5911.350s 30242.608us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_no_meas 5671.720s 28590.577us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 5842.950s 29429.592us 1 1 100.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 3276.470s 16482.402us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3291.850s 34417.919us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3291.850s 34417.919us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 154.350s 3388.432us 1 1 100.00
chip_sw_aes_enc_jitter_en 142.040s 2822.787us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 161.330s 2882.820us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 192.890s 2893.540us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 881.220s 7364.815us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 178.570s 2928.799us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 416.040s 6026.655us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 521.390s 6447.080us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 566.050s 5655.362us 1 1 100.00
chip_plic_all_irqs_10 252.830s 3544.902us 1 1 100.00
chip_plic_all_irqs_20 346.060s 4513.388us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 206.150s 3446.416us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 1175.910s 13565.933us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 211.970s 3120.525us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 166.140s 2721.405us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0.000s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 756.790s 6879.725us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 931.610s 7093.057us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 728.780s 7931.005us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 7645.940s 255103.110us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 220.640s 3338.272us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 259.450s 6435.306us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 220.640s 3338.272us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 478.280s 8217.180us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 478.280s 8217.180us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 325.140s 6425.125us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 368.840s 5611.907us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 619.290s 5936.944us 1 1 100.00
chip_sw_aes_idle 192.890s 2893.540us 1 1 100.00
chip_sw_hmac_enc_idle 166.520s 2881.041us 1 1 100.00
chip_sw_kmac_idle 135.950s 2754.343us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 327.540s 4544.374us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 330.920s 4942.303us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 218.930s 4123.705us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 279.040s 3801.492us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 920.120s 11995.134us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 426.030s 4355.727us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 379.670s 4498.593us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 384.230s 4437.389us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 359.530s 4421.592us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 382.530s 4751.609us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 362.770s 4727.425us 1 1 100.00
chip_sw_ast_clk_outputs 582.220s 8463.327us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 260.020s 6824.017us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 384.230s 4437.389us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 359.530s 4421.592us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 355.690s 3871.943us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 624.790s 5651.621us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3821.530s 19154.208us 1 1 100.00
chip_sw_aes_enc_jitter_en 142.040s 2822.787us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 832.880s 7747.307us 1 1 100.00
chip_sw_hmac_enc_jitter_en 206.540s 3226.343us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 562.110s 6298.860us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 182.190s 3136.394us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 347.510s 5428.571us 1 1 100.00
chip_sw_clkmgr_jitter 127.970s 2658.694us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 156.900s 2874.674us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 428.920s 4799.953us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 658.670s 7566.228us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 4040.890s 25028.044us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 143.840s 3403.748us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 181.920s 3655.921us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 995.560s 9268.601us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 197.310s 3532.407us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 323.950s 4310.353us 1 1 100.00
chip_sw_flash_init_reduced_freq 1157.860s 17830.484us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 13097.140s 146847.402us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 582.220s 8463.327us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 396.740s 5345.400us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 244.040s 3751.765us 1 1 100.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 521.390s 6447.080us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 756.790s 6879.725us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 2004.390s 23667.662us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 0 1 0.00
chip_sw_csrng_fuse_en_sw_app_read_test 179.060s 2820.219us 0 1 0.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 456.200s 7161.996us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 130.070s 2743.581us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 5520.720s 30952.622us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 120.190s 2549.255us 1 1 100.00
chip_sw_edn_entropy_reqs 779.380s 6540.155us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 120.190s 2549.255us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 2004.390s 23667.662us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 122.390s 2568.929us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 1106.190s 24006.610us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 531.370s 5267.589us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 624.790s 5651.621us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 393.520s 4562.946us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 355.690s 3871.943us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 3255.050s 43661.380us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 1106.190s 24006.610us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 238.190s 2935.121us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 1679.560s 12066.291us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 148.210s 2878.361us 0 1 0.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 3255.050s 43661.380us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 148.210s 2878.361us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 148.210s 2878.361us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 148.210s 2878.361us 0 1 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 148.210s 2878.361us 0 1 0.00
chip_sw_flash_lc_escalate_en 1 1 100.00
chip_sw_all_escalation_resets 521.390s 6447.080us 1 1 100.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 248.630s 9657.175us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 528.000s 5338.848us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 476.490s 6497.513us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 476.490s 6497.513us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 167.200s 3004.578us 1 1 100.00
chip_sw_hmac_enc_jitter_en 206.540s 3226.343us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 166.520s 2881.041us 1 1 100.00
chip_sw_hmac_all_configurations 1 1 100.00
chip_sw_hmac_oneshot 876.320s 6834.316us 1 1 100.00
chip_sw_hmac_multistream_mode 1 1 100.00
chip_sw_hmac_multistream 712.570s 5515.905us 1 1 100.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 306.770s 4664.229us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 377.010s 5044.727us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 354.750s 4962.418us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 266.540s 3440.315us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 1679.560s 12066.291us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 562.110s 6298.860us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 1764.950s 13306.081us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 881.220s 7364.815us 1 1 100.00
chip_sw_keymgr_sideload_otbn 1 1 100.00
chip_sw_keymgr_sideload_otbn 2152.320s 10809.443us 1 1 100.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 162.710s 3723.628us 1 1 100.00
chip_sw_kmac_mode_kmac 192.560s 3293.544us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 182.190s 3136.394us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 1679.560s 12066.291us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 740.190s 12682.896us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 139.000s 2986.654us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 993.340s 8081.943us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 135.950s 2754.343us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 416.040s 6026.655us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 81.770s 3010.514us 1 1 100.00
chip_tap_straps_rma 134.920s 3612.948us 1 1 100.00
chip_tap_straps_prod 711.780s 12163.720us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 164.740s 3083.634us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 740.190s 12682.896us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 740.190s 12682.896us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 740.190s 12682.896us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 1321.750s 10832.909us 1 1 100.00
chip_sw_lc_ctrl_broadcast 20 22 90.91
chip_sw_flash_ctrl_lc_rw_en 148.210s 2878.361us 0 1 0.00
chip_sw_flash_rma_unlocked 3255.050s 43661.380us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 240.920s 3153.105us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 423.350s 6111.212us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 437.900s 6830.414us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 519.040s 6445.603us 0 1 0.00
chip_sw_lc_ctrl_transition 740.190s 12682.896us 1 1 100.00
chip_sw_keymgr_key_derivation 1679.560s 12066.291us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 349.060s 9083.811us 1 1 100.00
chip_sw_sram_ctrl_execution_main 593.150s 10483.469us 1 1 100.00
chip_prim_tl_access 248.630s 9657.175us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 260.020s 6824.017us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 426.030s 4355.727us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 379.670s 4498.593us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 384.230s 4437.389us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 359.530s 4421.592us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 382.530s 4751.609us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 362.770s 4727.425us 1 1 100.00
chip_tap_straps_dev 81.770s 3010.514us 1 1 100.00
chip_tap_straps_rma 134.920s 3612.948us 1 1 100.00
chip_tap_straps_prod 711.780s 12163.720us 1 1 100.00
chip_rv_dm_lc_disabled 404.310s 12842.368us 1 1 100.00
chip_lc_scrap 4 4 100.00
chip_sw_lc_ctrl_rma_to_scrap 133.760s 3272.157us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 104.550s 2721.579us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 103.360s 3669.833us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 128.430s 2731.163us 1 1 100.00
chip_lc_test_locked 2 2 100.00
chip_sw_lc_walkthrough_testunlocks 1467.810s 26730.404us 1 1 100.00
chip_rv_dm_lc_disabled 404.310s 12842.368us 1 1 100.00
chip_sw_lc_walkthrough 2 5 40.00
chip_sw_lc_walkthrough_dev 637.700s 10908.712us 0 1 0.00
chip_sw_lc_walkthrough_prod 578.960s 8640.139us 0 1 0.00
chip_sw_lc_walkthrough_prodend 499.550s 8344.096us 1 1 100.00
chip_sw_lc_walkthrough_rma 354.420s 6293.010us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 1467.810s 26730.404us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 2 3 66.67
chip_sw_lc_ctrl_volatile_raw_unlock 78.060s 2209.815us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 55.620s 2163.501us 1 1 100.00
rom_volatile_raw_unlock 53.969s 0.000us 0 1 0.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 3593.120s 17294.428us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3821.530s 19154.208us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 619.290s 5936.944us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 619.290s 5936.944us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 619.290s 5936.944us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 339.500s 3781.765us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 740.190s 12682.896us 1 1 100.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 1106.190s 24006.610us 1 1 100.00
chip_sw_otbn_mem_scramble 339.500s 3781.765us 1 1 100.00
chip_sw_keymgr_key_derivation 1679.560s 12066.291us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 405.170s 5703.182us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 141.560s 2775.017us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 1106.190s 24006.610us 1 1 100.00
chip_sw_otbn_mem_scramble 339.500s 3781.765us 1 1 100.00
chip_sw_keymgr_key_derivation 1679.560s 12066.291us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 405.170s 5703.182us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 141.560s 2775.017us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 740.190s 12682.896us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 393.490s 6168.640us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 164.740s 3083.634us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 5 6 83.33
chip_sw_otp_ctrl_lc_signals_test_unlocked0 240.920s 3153.105us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 423.350s 6111.212us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 437.900s 6830.414us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 519.040s 6445.603us 0 1 0.00
chip_sw_lc_ctrl_transition 740.190s 12682.896us 1 1 100.00
chip_prim_tl_access 248.630s 9657.175us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 248.630s 9657.175us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 888.020s 8104.143us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 236.060s 5322.178us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 965.580s 23619.961us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 272.070s 7358.342us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 292.010s 7283.298us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 327.890s 5867.524us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1064.920s 26612.175us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 0 2 0.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 387.980s 9281.068us 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 478.280s 8217.180us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 742.510s 11557.897us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 364.310s 5117.034us 1 1 100.00
chip_sw_pwrmgr_aon_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 236.060s 5322.178us 0 1 0.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 282.020s 5002.760us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 428.150s 7446.834us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 299.070s 5959.938us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 112.660s 2620.118us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1416.410s 23011.411us 1 1 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 500.420s 6223.036us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1176.830s 13960.794us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 2001.690s 28866.849us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 143.530s 2902.354us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 521.390s 6447.080us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 349.060s 9083.811us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 349.060s 9083.811us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 4 4 100.00
chip_sw_pwrmgr_all_reset_reqs 1176.830s 13960.794us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1416.410s 23011.411us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 364.310s 5117.034us 1 1 100.00
chip_sw_pwrmgr_smoketest 259.450s 6435.306us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 318.990s 4597.603us 1 1 100.00
chip_sw_rstmgr_cpu_info 1 1 100.00
chip_sw_rstmgr_cpu_info 403.870s 5120.864us 1 1 100.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 323.450s 5258.742us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 1175.910s 13565.933us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 159.980s 2822.246us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 521.390s 6447.080us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 931.610s 7093.057us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 471.840s 5191.354us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 483.810s 5341.292us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 209.480s 3193.698us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 141.560s 2775.017us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 1 1 100.00
chip_sw_rstmgr_cpu_info 403.870s 5120.864us 1 1 100.00
chip_sw_rv_core_ibex_double_fault 1 1 100.00
chip_sw_rstmgr_cpu_info 403.870s 5120.864us 1 1 100.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 590.660s 9321.737us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 1002.370s 13724.275us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 318.990s 4597.603us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 165.040s 2970.257us 0 1 0.00
chip_rv_dm_access_after_wakeup 1 1 100.00
chip_sw_rv_dm_access_after_wakeup 351.820s 6337.579us 1 1 100.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 134.920s 3612.948us 1 1 100.00
chip_rv_dm_lc_disabled 1 1 100.00
chip_rv_dm_lc_disabled 404.310s 12842.368us 1 1 100.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 566.050s 5655.362us 1 1 100.00
chip_plic_all_irqs_10 252.830s 3544.902us 1 1 100.00
chip_plic_all_irqs_20 346.060s 4513.388us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 122.470s 2477.273us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 140.490s 3169.642us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 2978.490s 15339.172us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 469.610s 7007.644us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 192.430s 2577.601us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 209.070s 3494.726us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 211.200s 3458.989us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 405.170s 5703.182us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 347.510s 5428.571us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 527.400s 9462.960us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 352.910s 7682.152us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 593.150s 10483.469us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 521.390s 6447.080us 1 1 100.00
chip_sw_data_integrity_escalation 354.860s 6265.774us 1 1 100.00
chip_sw_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 500.420s 6223.036us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1017.640s 25328.669us 1 1 100.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 137.150s 2918.475us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 223.340s 3580.036us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 364.010s 4807.718us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 1 1 100.00
chip_sw_sysrst_ctrl_reset 1017.640s 25328.669us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_reset 1 1 100.00
chip_sw_sysrst_ctrl_reset 1017.640s 25328.669us 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2530.600s 21223.458us 1 1 100.00
chip_sw_sysrst_ctrl_flash_wp_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2530.600s 21223.458us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 286.280s 5491.933us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3291.850s 34417.919us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 122.470s 2979.515us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 142.190s 2849.780us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 238.640s 3786.420us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 357.540s 4489.452us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 1057.290s 9081.974us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 5458.630s 31899.734us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 1684.330s 12593.919us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 152.820s 2659.271us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 214.240s 3682.552us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 87.390s 2289.933us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 10145.980s 71622.789us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 1155.590s 6954.644us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 160.270s 4323.628us 0 1 0.00
rom_e2e_jtag_debug_dev 164.270s 3983.785us 0 1 0.00
rom_e2e_jtag_debug_rma 152.080s 4600.132us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 70.820s 2566.758us 0 1 0.00
rom_e2e_jtag_inject_dev 64.540s 2082.763us 0 1 0.00
rom_e2e_jtag_inject_rma 84.240s 2823.692us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 61.326s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 1 0.00
chip_sw_clkmgr_jitter_frequency 270.280s 3069.182us 0 1 0.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 296.280s 2759.039us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 507.010s 4415.293us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 1606.670s 11626.100us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 223.760s 2198.841us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 606.340s 5430.405us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 60.520s 2696.430us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 182.460s 2988.065us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 0 1 0.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 268.810s 5581.386us 0 1 0.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 298.930s 4927.220us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1176.830s 13960.794us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 160.270s 4323.628us 0 1 0.00
rom_e2e_jtag_debug_dev 164.270s 3983.785us 0 1 0.00
rom_e2e_jtag_debug_rma 152.080s 4600.132us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 389.900s 6428.378us 1 1 100.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 521.390s 6447.080us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 5651.190s 38283.157us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 5651.190s 38283.157us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 137.730s 3343.445us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 350.640s 4516.578us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 3175.950s 19734.823us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 8 10 80.00
chip_sival_flash_info_access 204.360s 3225.772us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 409.770s 5050.147us 1 1 100.00
chip_sw_otp_ctrl_rot_auth_config 4.880s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 131.620s 3387.084us 1 1 100.00
chip_sw_otp_ctrl_descrambling 197.510s 2591.497us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 273.060s 4211.757us 1 1 100.00
chip_sw_pwrmgr_sleep_wake_5_bug 8.335s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 172.040s 3326.873us 1 1 100.00
ate_bootstrap_flash_erase 6405.490s 44874.705us 1 1 100.00
ate_bootstrap_disjoint 10066.530s 84462.048us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*]
chip_sw_sleep_pin_mio_dio_val 73975470200196105083430175483815047805696119344720476512079500888293685024672 451
UVM_INFO @ 3225.034000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_spi_passthrough_collision_vseq.sv:183) virtual_sequencer [chip_sw_spi_passthrough_collision_vseq] Compare mismatch
chip_sw_spi_device_pass_through_collision 63726291757405554692074423509312333913771992596742524715649911472589589188980 322
host_rsp:
-------------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------------
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_flash_ctrl_lc_rw_en 60155771297676803277940543912531801475900348264017811571979007428538255056918 309
UVM_INFO @ 2878.360758 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *
chip_sw_otp_ctrl_lc_signals_rma 31429801080075851991407981766183048770437666119688856864253433982897331969881 342
UVM_INFO @ 6445.603240 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
chip_sw_otp_ctrl_escalation 34382972379786001516573791754200033570111178569005463834268131993017753396659 316
UVM_ERROR @ 2988.065080 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2988.065080 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_fuse_en_sw_app_read_test 59594728033468697466611450034660622507570911744855532135694113744649508176838 312
UVM_ERROR @ 2820.218628 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2820.218628 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode
chip_sw_otp_ctrl_rot_auth_config 39728833584203738806337943380664034415560327138628282435763662168502200573874 282
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_lc_walkthrough_dev 49562105420131946909420473112790786117256745544596674878853078758852892471019 369
UVM_INFO @ 10908.711714 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 68737491399158648748481608194548483618301502363979835244403840836759411636367 369
UVM_INFO @ 8640.139015 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 67860019011136826092501737110536112880118310344491178344977651199505252633102 341
UVM_INFO @ 6293.010205 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))'
chip_sw_pwrmgr_full_aon_reset 36362865895620625145790439785333497655131828919542327272402698689489137571697 322
UVM_ERROR @ 5322.177960 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 5322.177960 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 108437307774637304741911641299878416954099720011167918818572245575965424055076 327
UVM_ERROR @ 9281.068000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 9281.068000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 61657525043560915804922109059933348857382391410450298822781793560289716867589 325
UVM_ERROR @ 7283.298000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7283.298000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aon_timer_wdog_bite_reset 70837283344696964303520309278406008340809464164650650213350779002258117441160 319
UVM_ERROR @ 8217.180000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 8217.180000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))'
chip_sw_pwrmgr_sleep_power_glitch_reset 16006749461402713105629382631020176044095194822565059335727246165137376776289 313
UVM_ERROR @ 2620.118428 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 2620.118428 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 103421471132636511893483918369741512387450532549784049782366381488025686256267 327
UVM_ERROR @ 7446.834500 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 7446.834500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 101387586249223224425777874356588537906072397079658915277516258441268229081122 332
UVM_INFO @ 34417.919349 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:352)] CHECK-fail: Expect alert *!
chip_sw_alert_test 7129997477462992860820979184398366742047786775082740810681124972496961626768 307
UVM_INFO @ 2928.798908 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
chip_sw_alert_handler_lpg_sleep_mode_alerts 107370685935743801697811124854438052930540971206466774364668516944610321645200 308
UVM_INFO @ 2721.404992 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job killed!
chip_sw_alert_handler_lpg_sleep_mode_pings 52506912387547540028904833145202595707560747248015843048493162850082389124943 None
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *).
chip_tl_errors 28758084428187758637158857960090095868282973326838921632338459730984035454211 217
TL item was: req: (cip_tl_seq_item@34841) { a_addr: 'h10588 a_data: 'h16785d29 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3f a_opcode: 'h4 a_user: 'h1b6ce d_param: 'h0 d_source: 'h3f d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2622.624780 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 82154553988072710303193392289046693327417669352944946391558117602765423197526 224
TL item was: req: (cip_tl_seq_item@32415) { a_addr: 'h10374 a_data: 'hfe4d1d48 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hf a_opcode: 'h4 a_user: 'h192fe d_param: 'h0 d_source: 'hf d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1849.129532 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_clkmgr_jitter_frequency 87599292483251991543736073682247903417041749279948523736259978606803203109358 343
UVM_INFO @ 3069.181554 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']
chip_sw_pwrmgr_sleep_wake_5_bug 75671959421068131100047965725223687965280952191574812696300187520053445516855 None
---- STDERR ----
Another command (pid=2077323) is running. Waiting for it to complete on the server (server_pid=238765)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 45654171366416875946357153775105167504000854809752776759281664488934953068351 None
Another command (pid=357241) is running. Waiting for it to complete on the server (server_pid=238765)...
Another command (pid=367515) is running. Waiting for it to complete on the server (server_pid=238765)...
Another command (pid=433535) is running. Waiting for it to complete on the server (server_pid=238765)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_dev 31995953223385646245087134439658895815786089088094241532278248581432085333035 None
Another command (pid=570882) is running. Waiting for it to complete on the server (server_pid=238765)...
Another command (pid=848321) is running. Waiting for it to complete on the server (server_pid=238765)...
Another command (pid=849167) is running. Waiting for it to complete on the server (server_pid=238765)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod 22730403890956689505741561652683847321463698480535729187753379701654089039063 None
Another command (pid=574184) is running. Waiting for it to complete on the server (server_pid=238765)...
Another command (pid=511187) is running. Waiting for it to complete on the server (server_pid=238765)...
Another command (pid=546904) is running. Waiting for it to complete on the server (server_pid=238765)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 66550173598725346945307561693521948439331869075400427928080228600227666240258 None
Another command (pid=849167) is running. Waiting for it to complete on the server (server_pid=238765)...
Another command (pid=466926) is running. Waiting for it to complete on the server (server_pid=238765)...
Another command (pid=837702) is running. Waiting for it to complete on the server (server_pid=238765)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_rma 77899380979877468509505056152038622700780815821779909645367425791681693419889 None
---- STDERR ----
Another command (pid=450240) is running. Waiting for it to complete on the server (server_pid=238765)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 41662308859862870820352916347031981615414826999659972930099849018778793212322 None
Another command (pid=536703) is running. Waiting for it to complete on the server (server_pid=238765)...
Another command (pid=401091) is running. Waiting for it to complete on the server (server_pid=238765)...
Another command (pid=451177) is running. Waiting for it to complete on the server (server_pid=238765)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_dev 23890314024358503394348323614727360693946846804566532571477653763653042656485 None
Another command (pid=450240) is running. Waiting for it to complete on the server (server_pid=238765)...
Another command (pid=384511) is running. Waiting for it to complete on the server (server_pid=238765)...
Another command (pid=510841) is running. Waiting for it to complete on the server (server_pid=238765)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod 54224882453625291434391914161541810662121593625715127741606608874937719612392 None
Another command (pid=403576) is running. Waiting for it to complete on the server (server_pid=238765)...
Another command (pid=565434) is running. Waiting for it to complete on the server (server_pid=238765)...
Another command (pid=543832) is running. Waiting for it to complete on the server (server_pid=238765)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 82157881171497466963892728313973228271214056237760414379813659959127987760215 None
Another command (pid=468808) is running. Waiting for it to complete on the server (server_pid=238765)...
Another command (pid=452840) is running. Waiting for it to complete on the server (server_pid=238765)...
Another command (pid=510841) is running. Waiting for it to complete on the server (server_pid=238765)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_rma 53915064301095466935930107579462146620451314344294188747573416795706083489604 None
Another command (pid=633271) is running. Waiting for it to complete on the server (server_pid=238765)...
Another command (pid=634184) is running. Waiting for it to complete on the server (server_pid=238765)...
Another command (pid=586750) is running. Waiting for it to complete on the server (server_pid=238765)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 59008169800523134826046025640857150721009826710647745643972684692136686709371 None
Another command (pid=396401) is running. Waiting for it to complete on the server (server_pid=238765)...
Another command (pid=449397) is running. Waiting for it to complete on the server (server_pid=238765)...
Another command (pid=450240) is running. Waiting for it to complete on the server (server_pid=238765)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_dev 114163161797450316175460017519068351195927733378018619378526240351193031473855 None
---- STDERR ----
Another command (pid=450240) is running. Waiting for it to complete on the server (server_pid=238765)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod 113483167084460473657018838349724918700418210441241177899928059596976795793607 None
Another command (pid=539896) is running. Waiting for it to complete on the server (server_pid=238765)...
Another command (pid=542859) is running. Waiting for it to complete on the server (server_pid=238765)...
Another command (pid=552320) is running. Waiting for it to complete on the server (server_pid=238765)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 75737170445393136339769566947355459658808202190989076332188232670598251575484 None
Another command (pid=646415) is running. Waiting for it to complete on the server (server_pid=238765)...
Another command (pid=618918) is running. Waiting for it to complete on the server (server_pid=238765)...
Another command (pid=640347) is running. Waiting for it to complete on the server (server_pid=238765)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_rma 62814743119814499301401447234576265650225991204881008744821572718432671124658 None
Another command (pid=779647) is running. Waiting for it to complete on the server (server_pid=238765)...
Another command (pid=763981) is running. Waiting for it to complete on the server (server_pid=238765)...
Another command (pid=777547) is running. Waiting for it to complete on the server (server_pid=238765)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_test_unlocked0 32227476195467107367961331102941328555049283362533081314445555275324534905040 None
Another command (pid=367515) is running. Waiting for it to complete on the server (server_pid=238765)...
Another command (pid=433535) is running. Waiting for it to complete on the server (server_pid=238765)...
Another command (pid=435853) is running. Waiting for it to complete on the server (server_pid=238765)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_dev 78939756277987009892100010435503526140283342963892351444306167728661035925779 None
Another command (pid=528626) is running. Waiting for it to complete on the server (server_pid=238765)...
Another command (pid=536703) is running. Waiting for it to complete on the server (server_pid=238765)...
Another command (pid=401091) is running. Waiting for it to complete on the server (server_pid=238765)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod 11829521137576915092551513664307313527234879331481129544753365827868464306157 None
Another command (pid=367515) is running. Waiting for it to complete on the server (server_pid=238765)...
Another command (pid=433535) is running. Waiting for it to complete on the server (server_pid=238765)...
Another command (pid=378010) is running. Waiting for it to complete on the server (server_pid=238765)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod_end 82655726303079970130816717220202612948167685663071613616469478239426510855333 None
Another command (pid=367515) is running. Waiting for it to complete on the server (server_pid=238765)...
Another command (pid=433535) is running. Waiting for it to complete on the server (server_pid=238765)...
Another command (pid=371706) is running. Waiting for it to complete on the server (server_pid=238765)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_rma 58296138939304648115736912687351522854079227673649241434935574531336907531031 None
---- STDERR ----
Another command (pid=367515) is running. Waiting for it to complete on the server (server_pid=238765)...
Another command (pid=433535) is running. Waiting for it to complete on the server (server_pid=238765)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_volatile_raw_unlock 51890285086837933412537786788732597479920944277421059959603876530043722414915 None
Another command (pid=433535) is running. Waiting for it to complete on the server (server_pid=238765)...
Another command (pid=371706) is running. Waiting for it to complete on the server (server_pid=238765)...
Another command (pid=422841) is running. Waiting for it to complete on the server (server_pid=238765)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_raw_unlock 18452467613698635963780822508012814956358080772809587370147827938273066180694 None
Another command (pid=403977) is running. Waiting for it to complete on the server (server_pid=238765)...
Another command (pid=382965) is running. Waiting for it to complete on the server (server_pid=238765)...
Another command (pid=450240) is running. Waiting for it to complete on the server (server_pid=238765)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 53239028196345959500970531114322797710785644762565611554227556165088177422761 None
---- STDERR ----
Another command (pid=357241) is running. Waiting for it to complete on the server (server_pid=238765)...
Another command (pid=367515) is running. Waiting for it to complete on the server (server_pid=238765)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_sensor_ctrl_deep_sleep_wake_up_sim_dv(sw/device/tests/pwrmgr_sensor_ctrl_deep_sleep_wake_up.c:120)] CHECK-STATUS-fail: @@@:* = ErrorError
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 50353193936829038781084184267732558351330997433756926409543490306555388343879 317
UVM_INFO @ 5581.385628 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[NOA] Null object access
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 72725876157312286313417247288624184785748361387667994602224535336186943788899 327
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 93546991720071284341228919259134812573658196065136843230435839042957076515440 319
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 39301874787653832030852630642691587545611367805650697223200050553444734948889 305
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 75606253555220465265223932951410887855225390820286017974935357281880809548055 303
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 35049294427956114455475968696179393139970132656346961379125958660839819979991 305
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_idle_load 53443391216474202355696780931541456285583956166543904231889245834831172638625 312
UVM_INFO @ 3887.020000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_sleep_load 20079061557166482227557159401398840309710755157811217043324339093931190643075 319
UVM_INFO @ 3527.821000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *
chip_sw_ast_clk_rst_inputs 87936835516153854119732274451811338557009953008278885696815265466333104093969 327
UVM_INFO @ 9738.826225 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 4698819458714503684261585694427941883235463526605956390905241153946354692279 364
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 44702858948855790734950689791885390107684614749529193530803261231578324737911 325
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_dev 59202231364515889999392065319098474275447091851693956170092938792208168019690 367
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 73072403582503853626952065795240158062724456513609544018926209454811016994542 328
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_prod 6857001626024848545096863385532627213136348188344836541063313610550597037907 365
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 86945978112869456177360519529534405674508435770793429780099708473650765810982 363
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 49966995848619036277781493527390031612770099495522059559953257067024336726726 366
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 24328314371240070582089572608801207586984219917845098652706052254405001441333 328
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 69034015935865530234401543905819533766285430548014896231058132969833690428118 326
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 69561271504576237554340727358520561460781180059029453849724644778461524511466 326
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 61755195822853569549382659761319552423459244467874844730516613103155154622539 325
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_dev 59806495993269684712740846859516226016326643363152702172967237082791596468192 327
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_prod 37961494564975689351349865845083844161289439107842997871545160096355279126705 326
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 93567728393858580819309177238941191052645802164999876081297810764086238158418 327
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 93495863472352313025318139893907011185383022697204665085213235701690086401984 325
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_rv_debugger.sv:784) [debugger] Index * appears to be out of bounds
rom_e2e_jtag_debug_dev 79000929715358425265598970717184355378537539251434354999441662955247628162835 318
UVM_INFO @ 3983.784718 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_jtag_debug_rma 73034359951348927687296579665134133085579609862217227451551822349617510156941 318
UVM_INFO @ 4600.132250 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)'
rom_keymgr_functest 61620494117204977549722207605770530151346166651981297229789667514125578615760 327
UVM_ERROR @ 4304.420400 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 4304.420400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---