Simulation Results: clkmgr

 
29/04/2026 15:30:23 DVSim: v1.33.0 sha: a64a82b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.97 %
  • code
  • 98.18 %
  • assert
  • 95.48 %
  • func
  • 85.25 %
  • line
  • 98.99 %
  • branch
  • 98.62 %
  • cond
  • 94.11 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
91.67%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.890s 33.184us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.860s 23.395us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.850s 42.431us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 7.510s 1595.541us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.580s 75.483us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.170s 32.094us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.850s 42.431us 1 1 100.00
clkmgr_csr_aliasing 1.580s 75.483us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.950s 89.959us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.130s 57.906us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.760s 20.349us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.680s 18.422us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.890s 33.184us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 11.990s 2362.317us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 1.780s 262.359us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 11.990s 2362.317us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 16.840s 6842.546us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.880s 57.445us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 2.540s 132.494us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 2.540s 132.494us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.860s 23.395us 1 1 100.00
clkmgr_csr_rw 0.850s 42.431us 1 1 100.00
clkmgr_csr_aliasing 1.580s 75.483us 1 1 100.00
clkmgr_same_csr_outstanding 0.960s 34.495us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.860s 23.395us 1 1 100.00
clkmgr_csr_rw 0.850s 42.431us 1 1 100.00
clkmgr_csr_aliasing 1.580s 75.483us 1 1 100.00
clkmgr_same_csr_outstanding 0.960s 34.495us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 0.890s 8.565us 0 1 0.00
clkmgr_tl_intg_err 2.080s 220.403us 1 1 100.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.300s 133.562us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.300s 133.562us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.300s 133.562us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.300s 133.562us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 1.930s 291.173us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 2.080s 220.403us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 11.990s 2362.317us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 1.780s 262.359us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.300s 133.562us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.110s 209.360us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.770s 14.478us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 1.240s 258.568us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.910s 37.160us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.770s 17.931us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.850s 42.431us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 0.890s 8.565us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.850s 42.431us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.850s 42.431us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 0.890s 8.565us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 1.170s 208.572us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 52.410s 5412.934us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire
clkmgr_sec_cm 46957381798344914379203673830081994784158839246587640924691649096169327883914 84
UVM_INFO @ 8564606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---