Simulation Results: edn/edn0

 
29/04/2026 15:30:23 DVSim: v1.33.0 sha: a64a82b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.61 %
  • code
  • 81.25 %
  • assert
  • 95.01 %
  • func
  • 80.56 %
  • line
  • 97.23 %
  • branch
  • 90.52 %
  • cond
  • 84.62 %
  • toggle
  • 81.20 %
  • FSM
  • 52.69 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.930s 20.503us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.820s 49.749us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.850s 40.675us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.400s 74.739us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.170s 82.302us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.130s 112.499us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.850s 40.675us 1 1 100.00
edn_csr_aliasing 1.170s 82.302us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 0.910s 43.382us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 0.910s 43.382us 1 1 100.00
genbits 1 1 100.00
edn_genbits 0.910s 43.382us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.980s 68.332us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.180s 45.090us 1 1 100.00
errs 1 1 100.00
edn_err 0.910s 27.244us 1 1 100.00
disable 2 2 100.00
edn_disable 0.800s 11.619us 1 1 100.00
edn_disable_auto_req_mode 1.120s 90.207us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.980s 822.237us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.760s 18.551us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.800s 27.955us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.650s 97.518us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.650s 97.518us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.820s 49.749us 1 1 100.00
edn_csr_rw 0.850s 40.675us 1 1 100.00
edn_csr_aliasing 1.170s 82.302us 1 1 100.00
edn_same_csr_outstanding 0.970s 22.707us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.820s 49.749us 1 1 100.00
edn_csr_rw 0.850s 40.675us 1 1 100.00
edn_csr_aliasing 1.170s 82.302us 1 1 100.00
edn_same_csr_outstanding 0.970s 22.707us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 6.650s 1033.935us 1 1 100.00
edn_tl_intg_err 3.120s 457.547us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.890s 18.370us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.180s 45.090us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.650s 1033.935us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.650s 1033.935us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 6.650s 1033.935us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 6.650s 1033.935us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.180s 45.090us 1 1 100.00
edn_sec_cm 6.650s 1033.935us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.180s 45.090us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 3.120s 457.547us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 26.950s 6459.376us 1 1 100.00