Simulation Results: edn/edn1

 
29/04/2026 15:30:23 DVSim: v1.33.0 sha: a64a82b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.39 %
  • code
  • 83.32 %
  • assert
  • 97.14 %
  • func
  • 81.72 %
  • line
  • 98.33 %
  • branch
  • 93.72 %
  • cond
  • 89.54 %
  • toggle
  • 87.29 %
  • FSM
  • 47.73 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.020s 40.073us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.100s 14.857us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.000s 34.802us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.920s 175.701us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.400s 73.534us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.500s 46.418us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.000s 34.802us 1 1 100.00
edn_csr_aliasing 1.400s 73.534us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.590s 121.413us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.590s 121.413us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.590s 121.413us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.800s 58.643us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.200s 49.813us 1 1 100.00
errs 1 1 100.00
edn_err 1.210s 38.575us 1 1 100.00
disable 2 2 100.00
edn_disable 1.070s 13.904us 1 1 100.00
edn_disable_auto_req_mode 1.000s 37.624us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.870s 899.519us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.930s 16.446us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.920s 48.651us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.510s 104.809us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.510s 104.809us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.100s 14.857us 1 1 100.00
edn_csr_rw 1.000s 34.802us 1 1 100.00
edn_csr_aliasing 1.400s 73.534us 1 1 100.00
edn_same_csr_outstanding 0.850s 50.493us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.100s 14.857us 1 1 100.00
edn_csr_rw 1.000s 34.802us 1 1 100.00
edn_csr_aliasing 1.400s 73.534us 1 1 100.00
edn_same_csr_outstanding 0.850s 50.493us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 4.170s 1216.793us 1 1 100.00
edn_tl_intg_err 1.560s 195.951us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.980s 30.899us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.200s 49.813us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.170s 1216.793us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.170s 1216.793us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 4.170s 1216.793us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 4.170s 1216.793us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.200s 49.813us 1 1 100.00
edn_sec_cm 4.170s 1216.793us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.200s 49.813us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.560s 195.951us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 57.620s 52512.775us 1 1 100.00