Simulation Results: flash_ctrl

 
29/04/2026 15:30:23 DVSim: v1.33.0 sha: a64a82b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.41 %
  • code
  • 93.91 %
  • assert
  • 96.76 %
  • func
  • 95.57 %
  • line
  • 95.97 %
  • branch
  • 96.99 %
  • cond
  • 93.55 %
  • toggle
  • 97.99 %
  • FSM
  • 85.03 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 74.190s 114.551us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 14.630s 17.155us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 20.220s 52.571us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 5.850s 52.908us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 55.540s 4763.692us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 44.520s 1774.008us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 8.380s 86.232us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 5.850s 52.908us 1 1 100.00
flash_ctrl_csr_aliasing 44.520s 1774.008us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 13.800s 58.097us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 6.780s 23.374us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 16.490s 56.681us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 14.640s 122.889us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1254.660s 337652.248us 1 1 100.00
flash_ctrl_hw_rma_reset 559.010s 40122.288us 1 1 100.00
flash_ctrl_lcmgr_intg 9.770s 72.015us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1198.180s 298683.346us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 248.790s 13949.615us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 135.900s 3566.030us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 1716.180s 78240.357us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 109.390s 27085.088us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 12.290s 29.173us 1 1 100.00
flash_ctrl_rw_evict_all_en 12.960s 28.800us 1 1 100.00
flash_ctrl_re_evict 22.270s 79.886us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 45.760s 54.183us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 45.760s 54.183us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 96.320s 5105.706us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 12.330s 1574.909us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 30.600s 17.960us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 410.360s 9531.536us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 291.690s 1380.035us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 846.280s 845.630us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 6.180s 44.362us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 175.110s 24646.163us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 14.660s 49.808us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 7.580s 23.115us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 231.870s 487.024us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 159.920s 6093.490us 1 1 100.00
flash_ctrl_otp_reset 57.200s 81.674us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1254.660s 337652.248us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 143.790s 2118.973us 1 1 100.00
flash_ctrl_intr_wr 50.940s 2773.994us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 178.900s 25435.317us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 145.100s 49560.114us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 46.380s 1860.149us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 34.480s 2679.205us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 9.600s 124.093us 1 1 100.00
flash_ctrl_ro_derr 88.620s 546.640us 1 1 100.00
flash_ctrl_rw_derr 148.350s 3216.580us 1 1 100.00
flash_ctrl_derr_detect 127.080s 982.343us 1 1 100.00
flash_ctrl_integrity 321.080s 3770.695us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 9.030s 36.071us 1 1 100.00
flash_ctrl_ro_serr 106.980s 3194.273us 1 1 100.00
flash_ctrl_rw_serr 192.000s 17682.039us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 44.570s 2924.775us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 63.010s 3721.308us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 99.330s 4630.991us 1 1 100.00
flash_ctrl_write_word_sweep 7.140s 189.377us 1 1 100.00
flash_ctrl_read_word_sweep 10.410s 26.999us 1 1 100.00
flash_ctrl_ro 96.470s 1291.358us 1 1 100.00
flash_ctrl_rw 458.320s 4626.643us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 24.850s 3322.773us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 678.140s 82138.771us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 22.740s 10100.091us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 5.950s 246.560us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 9.070s 20.296us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 11.320s 136.951us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 11.320s 136.951us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 20.220s 52.571us 1 1 100.00
flash_ctrl_csr_rw 5.850s 52.908us 1 1 100.00
flash_ctrl_csr_aliasing 44.520s 1774.008us 1 1 100.00
flash_ctrl_same_csr_outstanding 9.060s 316.318us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 20.220s 52.571us 1 1 100.00
flash_ctrl_csr_rw 5.850s 52.908us 1 1 100.00
flash_ctrl_csr_aliasing 44.520s 1774.008us 1 1 100.00
flash_ctrl_same_csr_outstanding 9.060s 316.318us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 21.260s 70.209us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 21.260s 70.209us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 21.260s 70.209us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 21.260s 70.209us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 43.230s 276.128us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_sec_cm 1526.780s 2051.594us 1 1 100.00
flash_ctrl_tl_intg_err 372.300s 675.095us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 372.300s 675.095us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 372.300s 675.095us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 15.050s 215.555us 1 1 100.00
flash_ctrl_wr_intg 6.910s 47.010us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 74.190s 114.551us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 57.200s 81.674us 1 1 100.00
flash_ctrl_disable 14.660s 49.808us 1 1 100.00
flash_ctrl_sec_info_access 33.460s 2139.779us 1 1 100.00
flash_ctrl_connect 7.580s 23.115us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 8.760s 56.868us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 5.850s 52.908us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 21.260s 70.209us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 5.850s 52.908us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 21.260s 70.209us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 5.850s 52.908us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 21.260s 70.209us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 14.660s 49.808us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 15.050s 215.555us 1 1 100.00
flash_ctrl_access_after_disable 5.590s 66.551us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 18.520s 38.697us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 14.660s 49.808us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 12.330s 1574.909us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 458.320s 4626.643us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 192.000s 17682.039us 1 1 100.00
flash_ctrl_rw_derr 148.350s 3216.580us 1 1 100.00
flash_ctrl_integrity 321.080s 3770.695us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1254.660s 337652.248us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1526.780s 2051.594us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1526.780s 2051.594us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1526.780s 2051.594us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1526.780s 2051.594us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 10.950s 871.711us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 8.330s 26.082us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 6.290s 23.038us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1526.780s 2051.594us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1526.780s 2051.594us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1526.780s 2051.594us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 26.120s 250.350us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 214.670s 309.430us 1 1 100.00