Simulation Results: hmac

 
29/04/2026 15:30:23 DVSim: v1.33.0 sha: a64a82b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.18 %
  • code
  • 97.69 %
  • assert
  • 96.70 %
  • func
  • 43.16 %
  • line
  • 99.64 %
  • branch
  • 98.84 %
  • cond
  • 95.84 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 3.620s 269.319us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.840s 48.073us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 1.030s 301.911us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 5.140s 2312.677us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 6.630s 566.081us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 2.310s 32.633us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 1.030s 301.911us 1 1 100.00
hmac_csr_aliasing 6.630s 566.081us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 13.990s 10660.276us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 22.160s 1021.965us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 8.700s 361.543us 1 1 100.00
hmac_test_sha384_vectors 480.610s 13505.394us 1 1 100.00
hmac_test_sha512_vectors 382.060s 18990.453us 1 1 100.00
hmac_test_hmac256_vectors 6.790s 210.413us 1 1 100.00
hmac_test_hmac384_vectors 9.450s 1353.318us 1 1 100.00
hmac_test_hmac512_vectors 10.590s 1454.201us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 21.150s 10573.056us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 490.560s 3717.780us 1 1 100.00
error 1 1 100.00
hmac_error 28.400s 1362.999us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 34.950s 3116.571us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 3.620s 269.319us 1 1 100.00
hmac_long_msg 13.990s 10660.276us 1 1 100.00
hmac_back_pressure 22.160s 1021.965us 1 1 100.00
hmac_datapath_stress 490.560s 3717.780us 1 1 100.00
hmac_burst_wr 21.150s 10573.056us 1 1 100.00
hmac_stress_all 302.900s 43607.527us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 3.620s 269.319us 1 1 100.00
hmac_long_msg 13.990s 10660.276us 1 1 100.00
hmac_back_pressure 22.160s 1021.965us 1 1 100.00
hmac_datapath_stress 490.560s 3717.780us 1 1 100.00
hmac_wipe_secret 34.950s 3116.571us 1 1 100.00
hmac_test_sha256_vectors 8.700s 361.543us 1 1 100.00
hmac_test_sha384_vectors 480.610s 13505.394us 1 1 100.00
hmac_test_sha512_vectors 382.060s 18990.453us 1 1 100.00
hmac_test_hmac256_vectors 6.790s 210.413us 1 1 100.00
hmac_test_hmac384_vectors 9.450s 1353.318us 1 1 100.00
hmac_test_hmac512_vectors 10.590s 1454.201us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 3.620s 269.319us 1 1 100.00
hmac_long_msg 13.990s 10660.276us 1 1 100.00
hmac_back_pressure 22.160s 1021.965us 1 1 100.00
hmac_datapath_stress 490.560s 3717.780us 1 1 100.00
hmac_burst_wr 21.150s 10573.056us 1 1 100.00
hmac_error 28.400s 1362.999us 1 1 100.00
hmac_wipe_secret 34.950s 3116.571us 1 1 100.00
hmac_test_sha256_vectors 8.700s 361.543us 1 1 100.00
hmac_test_sha384_vectors 480.610s 13505.394us 1 1 100.00
hmac_test_sha512_vectors 382.060s 18990.453us 1 1 100.00
hmac_test_hmac256_vectors 6.790s 210.413us 1 1 100.00
hmac_test_hmac384_vectors 9.450s 1353.318us 1 1 100.00
hmac_test_hmac512_vectors 10.590s 1454.201us 1 1 100.00
hmac_stress_all 302.900s 43607.527us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 302.900s 43607.527us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.650s 19.978us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.630s 24.614us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 1.640s 88.934us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 1.640s 88.934us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.840s 48.073us 1 1 100.00
hmac_csr_rw 1.030s 301.911us 1 1 100.00
hmac_csr_aliasing 6.630s 566.081us 1 1 100.00
hmac_same_csr_outstanding 1.980s 112.053us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.840s 48.073us 1 1 100.00
hmac_csr_rw 1.030s 301.911us 1 1 100.00
hmac_csr_aliasing 6.630s 566.081us 1 1 100.00
hmac_same_csr_outstanding 1.980s 112.053us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.020s 107.310us 1 1 100.00
hmac_tl_intg_err 2.760s 778.192us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.760s 778.192us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 3.620s 269.319us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 3.340s 217.755us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 266.420s 14721.558us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.210s 51.456us 1 1 100.00