Simulation Results

Simulation Results: i2c

29/04/2026 15:30:23 DVSim: v1.33.0 sha: a64a82b json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
85.17 %

code
80.78 %

assert
96.41 %

func
78.33 %

line
95.95 %

branch
91.70 %

cond
84.93 %

toggle
89.66 %

FSM
41.67 %

Validation stages

V1		100.00%
V2		87.80%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	20.440s	10431.605us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	11.680s	4734.793us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.990s	117.307us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.890s	25.674us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	3.740s	713.800us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.520s	96.167us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	0.900s	18.539us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.890s	25.674us	1	1	100.00
	i2c_csr_aliasing	1.520s	96.167us	1	1	100.00

36/41 passed

87.80 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	1.150s	32.829us	0	1	0.00
host_stress_all				1	1	100.00
	i2c_host_stress_all	2184.070s	115927.039us	1	1	100.00
host_maxperf				1	1	100.00
	i2c_host_perf	657.230s	18295.050us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.770s	49.751us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	46.140s	3181.807us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	52.270s	8302.075us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	0.770s	133.069us	1	1	100.00
	i2c_host_fifo_fmt_empty	3.020s	559.327us	1	1	100.00
	i2c_host_fifo_reset_rx	4.300s	219.927us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	60.220s	3861.229us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	9.970s	7080.460us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	0.730s	21.322us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	1.940s	473.403us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	192.550s	34822.291us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	2.860s	2138.709us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	12.990s	4142.264us	1	1	100.00
	i2c_target_intr_smoke	3.700s	3593.120us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	1.650s	880.316us	1	1	100.00
	i2c_target_fifo_reset_tx	1.110s	407.384us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	11.970s	22352.264us	1	1	100.00
	i2c_target_stress_rd	12.990s	4142.264us	1	1	100.00
	i2c_target_intr_stress_wr	37.880s	23469.889us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	4.980s	1117.435us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	22.850s	916.129us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	2.970s	3844.688us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	7.390s	10245.161us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	1.880s	1387.694us	1	1	100.00
	i2c_target_fifo_watermarks_tx	1.140s	458.440us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	657.230s	18295.050us	1	1	100.00
	i2c_host_perf_precise	1.000s	257.839us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	9.970s	7080.460us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	4.280s	166.968us	1	1	100.00
target_mode_nack_generation				2	3	66.67
	i2c_target_nack_acqfull	2.320s	2418.581us	1	1	100.00
	i2c_target_nack_acqfull_addr	2.100s	2577.443us	1	1	100.00
	i2c_target_nack_txstretch	1.500s	125.274us	0	1	0.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	18.050s	658.428us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.700s	1926.741us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.670s	32.529us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.890s	17.288us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	2.740s	2140.250us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	2.740s	2140.250us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.990s	117.307us	1	1	100.00
	i2c_csr_rw	0.890s	25.674us	1	1	100.00
	i2c_csr_aliasing	1.520s	96.167us	1	1	100.00
	i2c_same_csr_outstanding	0.950s	153.162us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.990s	117.307us	1	1	100.00
	i2c_csr_rw	0.890s	25.674us	1	1	100.00
	i2c_csr_aliasing	1.520s	96.167us	1	1	100.00
	i2c_same_csr_outstanding	0.950s	153.162us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.610s	1007.949us	1	1	100.00
	i2c_sec_cm	1.210s	130.801us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.610s	1007.949us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	4.030s	111.543us	1
target_error_intr				1
	i2c_target_unexp_stop	2.050s	3317.571us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	0.810s	67.535us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
	i2c_host_error_intr	13279946234082198001742104002382678383795188653839947162367714189309392228295	80	UVM_INFO @ 32829157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	94154984028200574940095798971824506275461570025155862890816253319051325448290	93	UVM_INFO @ 67535020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
	i2c_target_glitch	66164409571374850684918717139534699924754301057724953559191515837281634509095	84	UVM_INFO @ 473402925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
	i2c_target_unexp_stop	33325869895605985621965968547869610987708727971962518895913177587025452087020	79	UVM_ERROR @ 3317571384 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A UVM_INFO @ 3317571384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
	i2c_target_hrst	88370819021021668734718738220780640638388319795269381226880184068637043997562	79	UVM_INFO @ 10245160632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
	i2c_host_stress_all_with_rand_reset	47048992189461789868430620156505860830685448067517825673267669022279449582382	84	UVM_INFO @ 111542961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=, Comparison=CompareOpEq, exp_data=, call_count=3)
	i2c_host_mode_toggle	113137694782957597298217756541784650870346759142876946725481569261582657058100	79	UVM_INFO @ 21321890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: i2c_reg_block.target_nack_count reset value:
	i2c_target_nack_txstretch	67973277585829494379189950030657204272947432187564733458299113849391994049516	78	UVM_INFO @ 125274080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---