Simulation Results: kmac/masked

 
29/04/2026 15:30:23 DVSim: v1.33.0 sha: a64a82b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.77 %
  • code
  • 90.77 %
  • assert
  • 97.98 %
  • func
  • 95.56 %
  • line
  • 98.91 %
  • branch
  • 96.63 %
  • cond
  • 93.88 %
  • toggle
  • 99.65 %
  • FSM
  • 64.79 %
Validation stages
V1
100.00%
V2
96.55%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 44.490s 1637.082us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 0.900s 74.783us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 0.930s 15.855us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 7.530s 507.618us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 3.630s 890.959us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 2.070s 297.989us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 0.930s 15.855us 1 1 100.00
kmac_csr_aliasing 3.630s 890.959us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.860s 13.527us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.240s 49.929us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 129.410s 23924.806us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 328.310s 4390.769us 1 1 100.00
test_vectors 7 8 87.50
kmac_test_vectors_sha3_224 28.180s 1289.113us 1 1 100.00
kmac_test_vectors_sha3_256 33.060s 12994.192us 1 1 100.00
kmac_test_vectors_sha3_384 21.820s 1515.125us 1 1 100.00
kmac_test_vectors_sha3_512 0.980s 66.262us 0 1 0.00
kmac_test_vectors_shake_128 193.130s 58734.366us 1 1 100.00
kmac_test_vectors_shake_256 318.540s 111827.329us 1 1 100.00
kmac_test_vectors_kmac 3.200s 336.080us 1 1 100.00
kmac_test_vectors_kmac_xof 2.690s 216.928us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 15.390s 714.827us 1 1 100.00
app 1 1 100.00
kmac_app 199.940s 17649.996us 1 1 100.00
app_with_partial_data 1 1 100.00
kmac_app_with_partial_data 95.760s 13649.611us 1 1 100.00
entropy_refresh 1 1 100.00
kmac_entropy_refresh 47.390s 1188.381us 1 1 100.00
error 1 1 100.00
kmac_error 309.710s 22931.801us 1 1 100.00
key_error 1 1 100.00
kmac_key_error 5.580s 2530.828us 1 1 100.00
sideload_invalid 1 1 100.00
kmac_sideload_invalid 6.270s 464.766us 1 1 100.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 1.110s 50.303us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 18.980s 985.094us 1 1 100.00
entropy_ready_error 1 1 100.00
kmac_entropy_ready_error 32.050s 3862.817us 1 1 100.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.330s 72.704us 1 1 100.00
stress_all 1 1 100.00
kmac_stress_all 910.990s 176703.149us 1 1 100.00
intr_test 1 1 100.00
kmac_intr_test 0.750s 50.878us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 0.880s 33.200us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 2.480s 240.893us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 2.480s 240.893us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 0.900s 74.783us 1 1 100.00
kmac_csr_rw 0.930s 15.855us 1 1 100.00
kmac_csr_aliasing 3.630s 890.959us 1 1 100.00
kmac_same_csr_outstanding 1.470s 78.776us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 0.900s 74.783us 1 1 100.00
kmac_csr_rw 0.930s 15.855us 1 1 100.00
kmac_csr_aliasing 3.630s 890.959us 1 1 100.00
kmac_same_csr_outstanding 1.470s 78.776us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.550s 65.747us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.550s 65.747us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.550s 65.747us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.550s 65.747us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 4.040s 973.031us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 34.140s 12581.197us 1 1 100.00
kmac_tl_intg_err 3.310s 365.883us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 3.310s 365.883us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.330s 72.704us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 44.490s 1637.082us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 15.390s 714.827us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.550s 65.747us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 34.140s 12581.197us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 34.140s 12581.197us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 34.140s 12581.197us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 44.490s 1637.082us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.330s 72.704us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 34.140s 12581.197us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 1 1 100.00
kmac_mubi 173.920s 11173.650us 1 1 100.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 44.490s 1637.082us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
kmac_stress_all_with_rand_reset 132.330s 6186.247us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: *
kmac_test_vectors_sha3_512 16901492038258857859361708611434463962533365023543416905603903022661523306742 78
UVM_INFO @ 66261568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---