Simulation Results: lc_ctrl/volatile_unlock_disabled

 
29/04/2026 15:30:23 DVSim: v1.33.0 sha: a64a82b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.86 %
  • code
  • 84.33 %
  • assert
  • 94.13 %
  • func
  • 94.13 %
  • line
  • 97.26 %
  • branch
  • 93.97 %
  • cond
  • 78.74 %
  • toggle
  • 87.17 %
  • FSM
  • 64.49 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.250s 17.672us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.100s 21.582us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.920s 48.630us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.340s 41.622us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.510s 146.896us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.160s 38.342us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.920s 48.630us 1 1 100.00
lc_ctrl_csr_aliasing 1.510s 146.896us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.450s 225.304us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 5.410s 1172.807us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.970s 17.099us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.930s 51.422us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 9.560s 271.198us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 6.330s 376.663us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 9.560s 271.198us 1 1 100.00
lc_ctrl_prog_failure 2.930s 51.422us 1 1 100.00
lc_ctrl_errors 6.330s 376.663us 1 1 100.00
lc_ctrl_security_escalation 7.870s 1157.675us 1 1 100.00
lc_ctrl_jtag_state_failure 33.110s 1483.457us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.050s 418.762us 1 1 100.00
lc_ctrl_jtag_errors 26.630s 1294.079us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.910s 1291.663us 1 1 100.00
lc_ctrl_jtag_state_post_trans 16.290s 1941.619us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.050s 418.762us 1 1 100.00
lc_ctrl_jtag_errors 26.630s 1294.079us 1 1 100.00
lc_ctrl_jtag_access 4.610s 152.272us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 26.420s 4646.070us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.190s 171.930us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.260s 63.654us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 4.060s 1808.961us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 5.460s 979.059us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.460s 24.891us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.400s 174.148us 1 1 100.00
lc_ctrl_jtag_alert_test 2.130s 398.998us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 1.960s 208.726us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.010s 56.645us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 176.630s 62746.413us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.160s 26.996us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.830s 160.130us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.830s 160.130us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.100s 21.582us 1 1 100.00
lc_ctrl_csr_rw 0.920s 48.630us 1 1 100.00
lc_ctrl_csr_aliasing 1.510s 146.896us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.600s 46.488us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.100s 21.582us 1 1 100.00
lc_ctrl_csr_rw 0.920s 48.630us 1 1 100.00
lc_ctrl_csr_aliasing 1.510s 146.896us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.600s 46.488us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 7.640s 1403.341us 1 1 100.00
lc_ctrl_tl_intg_err 1.980s 223.953us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.980s 223.953us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 5.410s 1172.807us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 9.560s 271.198us 1 1 100.00
lc_ctrl_sec_cm 7.640s 1403.341us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 9.560s 271.198us 1 1 100.00
lc_ctrl_sec_cm 7.640s 1403.341us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.560s 271.198us 1 1 100.00
lc_ctrl_sec_cm 7.640s 1403.341us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.560s 271.198us 1 1 100.00
lc_ctrl_sec_cm 7.640s 1403.341us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 9.560s 271.198us 1 1 100.00
lc_ctrl_sec_cm 7.640s 1403.341us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.560s 271.198us 1 1 100.00
lc_ctrl_sec_cm 7.640s 1403.341us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.560s 271.198us 1 1 100.00
lc_ctrl_sec_cm 7.640s 1403.341us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 9.560s 271.198us 1 1 100.00
lc_ctrl_sec_cm 7.640s 1403.341us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 7.870s 1157.675us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.450s 225.304us 1 1 100.00
lc_ctrl_jtag_state_post_trans 16.290s 1941.619us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 9.620s 895.531us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 9.620s 895.531us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 14.860s 1792.156us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 9.090s 406.497us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 9.090s 406.497us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 24.920s 9531.959us 1 1 100.00