Simulation Results: lc_ctrl/volatile_unlock_enabled

 
29/04/2026 15:30:23 DVSim: v1.33.0 sha: a64a82b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.42 %
  • code
  • 84.18 %
  • assert
  • 93.85 %
  • func
  • 93.24 %
  • line
  • 97.10 %
  • branch
  • 93.62 %
  • cond
  • 79.56 %
  • toggle
  • 87.05 %
  • FSM
  • 63.55 %
Validation stages
V1
100.00%
V2
96.67%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.310s 162.499us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.840s 14.235us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.870s 90.596us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.990s 801.012us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.380s 16.286us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.020s 51.552us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.870s 90.596us 1 1 100.00
lc_ctrl_csr_aliasing 1.380s 16.286us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.900s 64.637us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 9.670s 806.966us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.980s 13.757us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.130s 198.389us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.370s 843.381us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 7.420s 302.207us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 7.370s 843.381us 1 1 100.00
lc_ctrl_prog_failure 2.130s 198.389us 1 1 100.00
lc_ctrl_errors 7.420s 302.207us 1 1 100.00
lc_ctrl_security_escalation 5.990s 365.787us 1 1 100.00
lc_ctrl_jtag_state_failure 26.810s 10280.198us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.700s 1940.420us 1 1 100.00
lc_ctrl_jtag_errors 21.210s 2078.323us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 4.490s 2961.010us 1 1 100.00
lc_ctrl_jtag_state_post_trans 18.640s 1530.152us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.700s 1940.420us 1 1 100.00
lc_ctrl_jtag_errors 21.210s 2078.323us 1 1 100.00
lc_ctrl_jtag_access 2.820s 577.862us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 12.860s 2013.009us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.390s 361.621us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.350s 78.402us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 15.330s 6801.059us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.300s 789.806us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.570s 36.282us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.480s 1191.973us 1 1 100.00
lc_ctrl_jtag_alert_test 1.450s 189.562us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 5.210s 238.907us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.220s 52.500us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 83.440s 4026.191us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.010s 50.755us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.150s 433.844us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.150s 433.844us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.840s 14.235us 1 1 100.00
lc_ctrl_csr_rw 0.870s 90.596us 1 1 100.00
lc_ctrl_csr_aliasing 1.380s 16.286us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.970s 100.169us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.840s 14.235us 1 1 100.00
lc_ctrl_csr_rw 0.870s 90.596us 1 1 100.00
lc_ctrl_csr_aliasing 1.380s 16.286us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.970s 100.169us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 8.130s 433.205us 1 1 100.00
lc_ctrl_tl_intg_err 1.500s 223.599us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.500s 223.599us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 9.670s 806.966us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.370s 843.381us 1 1 100.00
lc_ctrl_sec_cm 8.130s 433.205us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.370s 843.381us 1 1 100.00
lc_ctrl_sec_cm 8.130s 433.205us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.370s 843.381us 1 1 100.00
lc_ctrl_sec_cm 8.130s 433.205us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.370s 843.381us 1 1 100.00
lc_ctrl_sec_cm 8.130s 433.205us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.370s 843.381us 1 1 100.00
lc_ctrl_sec_cm 8.130s 433.205us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.370s 843.381us 1 1 100.00
lc_ctrl_sec_cm 8.130s 433.205us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.370s 843.381us 1 1 100.00
lc_ctrl_sec_cm 8.130s 433.205us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.370s 843.381us 1 1 100.00
lc_ctrl_sec_cm 8.130s 433.205us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.990s 365.787us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.900s 64.637us 1 1 100.00
lc_ctrl_jtag_state_post_trans 18.640s 1530.152us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 8.730s 743.907us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 8.730s 743.907us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 12.910s 1640.504us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.180s 423.957us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.180s 423.957us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 39.380s 3272.570us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*])
lc_ctrl_stress_all 1969036066532296879396868251749443846875355063166823541222249278529422691923 4694
UVM_INFO @ 4026190590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---