Simulation Results: otp_ctrl

 
29/04/2026 15:30:23 DVSim: v1.33.0 sha: a64a82b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.58 %
  • code
  • 78.31 %
  • assert
  • 94.11 %
  • func
  • 72.33 %
  • line
  • 88.92 %
  • branch
  • 84.11 %
  • cond
  • 92.32 %
  • toggle
  • 84.86 %
  • FSM
  • 41.32 %
Validation stages
V1
100.00%
V2
85.00%
V2S
77.78%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.970s 106.809us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 5.160s 499.848us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.750s 146.086us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.440s 161.859us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 11.180s 6324.188us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 3.380s 384.463us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.710s 104.252us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.440s 161.859us 1 1 100.00
otp_ctrl_csr_aliasing 3.380s 384.463us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.660s 76.139us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.390s 139.021us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 13.590s 318.105us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 3.510s 666.078us 1 1 100.00
partition_check 1 2 50.00
otp_ctrl_background_chks 23.320s 4741.013us 1 1 100.00
otp_ctrl_check_fail 5.580s 292.528us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 7.300s 315.213us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 9.150s 756.499us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 13.790s 1100.226us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 18.320s 920.765us 1 1 100.00
otp_ctrl_parallel_lc_esc 8.360s 539.666us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 24.770s 9036.976us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 1.980s 179.755us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 4.730s 1817.109us 1 1 100.00
stress_all 0 1 0.00
otp_ctrl_stress_all 66.780s 15752.383us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.300s 588.752us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.960s 123.436us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 4.170s 106.363us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 4.170s 106.363us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.750s 146.086us 1 1 100.00
otp_ctrl_csr_rw 1.440s 161.859us 1 1 100.00
otp_ctrl_csr_aliasing 3.380s 384.463us 1 1 100.00
otp_ctrl_same_csr_outstanding 1.910s 51.437us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.750s 146.086us 1 1 100.00
otp_ctrl_csr_rw 1.440s 161.859us 1 1 100.00
otp_ctrl_csr_aliasing 3.380s 384.463us 1 1 100.00
otp_ctrl_same_csr_outstanding 1.910s 51.437us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 119.580s 14180.327us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 119.580s 14180.327us 1 1 100.00
otp_ctrl_tl_intg_err 14.050s 5018.194us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 119.580s 14180.327us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 119.580s 14180.327us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 14.050s 5018.194us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 5.160s 499.848us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 5.160s 499.848us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 119.580s 14180.327us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 119.580s 14180.327us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 119.580s 14180.327us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 119.580s 14180.327us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 119.580s 14180.327us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 119.580s 14180.327us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 119.580s 14180.327us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 119.580s 14180.327us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 119.580s 14180.327us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 119.580s 14180.327us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 119.580s 14180.327us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 119.580s 14180.327us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 119.580s 14180.327us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 119.580s 14180.327us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 119.580s 14180.327us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 8.360s 539.666us 1 1 100.00
otp_ctrl_sec_cm 119.580s 14180.327us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 8.360s 539.666us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 8.360s 539.666us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 8.360s 539.666us 1 1 100.00
otp_ctrl_macro_errs 1.980s 179.755us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 8.360s 539.666us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 8.360s 539.666us 1 1 100.00
otp_ctrl_sec_cm 119.580s 14180.327us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 8.360s 539.666us 1 1 100.00
otp_ctrl_sec_cm 119.580s 14180.327us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 8.360s 539.666us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 8.360s 539.666us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 8.360s 539.666us 1 1 100.00
otp_ctrl_macro_errs 1.980s 179.755us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 8.360s 539.666us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 8.360s 539.666us 1 1 100.00
otp_ctrl_sec_cm 119.580s 14180.327us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 3.510s 666.078us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 5.580s 292.528us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 9.150s 756.499us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 9.150s 756.499us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 9.150s 756.499us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 9.150s 756.499us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 9.150s 756.499us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 5.160s 499.848us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 9.150s 756.499us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 5.160s 499.848us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 119.580s 14180.327us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 7.300s 315.213us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 5.160s 499.848us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 5.160s 499.848us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 1.980s 179.755us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 9.660s 5904.880us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
otp_ctrl_stress_all_with_rand_reset 93.710s 73910.432us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_*
otp_ctrl_check_fail 99812310623326713579376766341526680994488550412916834470053050041052196793592 3831
UVM_INFO @ 292528446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 36747727760858495581382674381584078524236274145776391529826534366162961970657 333
UVM_INFO @ 179754894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1315) [otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_check_error does not trigger!
otp_ctrl_stress_all 90322528055731724836371250820965387260380028566048130835059747595263990376487 28120
UVM_INFO @ 15752382678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---