Simulation Results: pattgen

 
29/04/2026 15:30:23 DVSim: v1.33.0 sha: a64a82b json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.08 %
  • code
  • 98.87 %
  • assert
  • 96.95 %
  • func
  • 89.42 %
  • block
  • 100.00 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • toggle
  • 96.61 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pattgen_smoke 2.000s 129.829us 1 1 100.00
csr_hw_reset 1 1 100.00
pattgen_csr_hw_reset 1.000s 25.424us 1 1 100.00
csr_rw 1 1 100.00
pattgen_csr_rw 1.000s 69.529us 1 1 100.00
csr_bit_bash 1 1 100.00
pattgen_csr_bit_bash 2.000s 1334.725us 1 1 100.00
csr_aliasing 1 1 100.00
pattgen_csr_aliasing 1.000s 32.204us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pattgen_csr_mem_rw_with_rand_reset 1.000s 75.122us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pattgen_csr_rw 1.000s 69.529us 1 1 100.00
pattgen_csr_aliasing 1.000s 32.204us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
perf 1 1 100.00
pattgen_perf 32.000s 1447.585us 1 1 100.00
cnt_rollover 1 1 100.00
cnt_rollover 28.000s 2466.426us 1 1 100.00
error 1 1 100.00
pattgen_error 1.000s 59.774us 1 1 100.00
stress_all 1 1 100.00
pattgen_stress_all 1.000s 21.711us 1 1 100.00
alert_test 1 1 100.00
pattgen_alert_test 2.000s 14.367us 1 1 100.00
intr_test 1 1 100.00
pattgen_intr_test 1.000s 16.523us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pattgen_tl_errors 1.000s 176.206us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pattgen_tl_errors 1.000s 176.206us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 25.424us 1 1 100.00
pattgen_csr_rw 1.000s 69.529us 1 1 100.00
pattgen_csr_aliasing 1.000s 32.204us 1 1 100.00
pattgen_same_csr_outstanding 2.000s 118.904us 1 1 100.00
tl_d_partial_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 25.424us 1 1 100.00
pattgen_csr_rw 1.000s 69.529us 1 1 100.00
pattgen_csr_aliasing 1.000s 32.204us 1 1 100.00
pattgen_same_csr_outstanding 2.000s 118.904us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pattgen_tl_intg_err 1.000s 99.246us 1 1 100.00
pattgen_sec_cm 1.000s 92.102us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pattgen_tl_intg_err 1.000s 99.246us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
pattgen_stress_all_with_rand_reset 19.000s 5497.053us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
pattgen_inactive_level 2.000s 98.394us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1237) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
pattgen_stress_all_with_rand_reset 106692133116080513506186692661928812003755156185084419406513321399721714301196 212
UVM_ERROR @ 1864756224 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1864756224 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 3/5
UVM_INFO @ 1864856224 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]