Simulation Results: rom_ctrl/64kb

 
29/04/2026 15:30:23 DVSim: v1.33.0 sha: a64a82b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.27 %
  • code
  • 97.87 %
  • assert
  • 96.80 %
  • func
  • 97.14 %
  • line
  • 99.46 %
  • branch
  • 99.27 %
  • cond
  • 97.47 %
  • toggle
  • 99.82 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 7.720s 226.930us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 10.450s 742.559us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 5.700s 698.331us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 9.180s 3970.285us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 7.400s 302.146us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 5.940s 783.983us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 5.700s 698.331us 1 1 100.00
rom_ctrl_csr_aliasing 7.400s 302.146us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 6.060s 386.819us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 6.500s 287.023us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 7.450s 258.647us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 19.890s 2175.812us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 16.480s 2952.722us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 5.710s 1687.226us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 7.690s 383.683us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 7.690s 383.683us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 10.450s 742.559us 1 1 100.00
rom_ctrl_csr_rw 5.700s 698.331us 1 1 100.00
rom_ctrl_csr_aliasing 7.400s 302.146us 1 1 100.00
rom_ctrl_same_csr_outstanding 9.580s 220.192us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 10.450s 742.559us 1 1 100.00
rom_ctrl_csr_rw 5.700s 698.331us 1 1 100.00
rom_ctrl_csr_aliasing 7.400s 302.146us 1 1 100.00
rom_ctrl_same_csr_outstanding 9.580s 220.192us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 175.090s 19440.129us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 23.460s 2761.830us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 447.670s 1261.593us 1 1 100.00
rom_ctrl_tl_intg_err 97.210s 393.583us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 447.670s 1261.593us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 447.670s 1261.593us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 175.090s 19440.129us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 175.090s 19440.129us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 175.090s 19440.129us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 175.090s 19440.129us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 175.090s 19440.129us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 447.670s 1261.593us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 447.670s 1261.593us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 7.720s 226.930us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 7.720s 226.930us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 7.720s 226.930us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 97.210s 393.583us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 175.090s 19440.129us 1 1 100.00
rom_ctrl_kmac_err_chk 16.480s 2952.722us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 175.090s 19440.129us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 175.090s 19440.129us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 175.090s 19440.129us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 23.460s 2761.830us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 447.670s 1261.593us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 55.570s 3587.193us 1 1 100.00