Simulation Results: rstmgr

 
29/04/2026 15:30:23 DVSim: v1.33.0 sha: a64a82b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.26 %
  • code
  • 99.28 %
  • assert
  • 97.99 %
  • func
  • 97.51 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.26 %
  • toggle
  • 99.50 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.180s 124.208us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.110s 152.618us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.830s 68.911us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 5.570s 478.241us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.750s 164.066us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.620s 183.656us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.830s 68.911us 1 1 100.00
rstmgr_csr_aliasing 1.750s 164.066us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.790s 164.365us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.920s 371.235us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.130s 159.316us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.410s 1500.843us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.410s 1500.843us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.410s 1500.843us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.410s 1500.843us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 16.610s 6489.127us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.890s 75.331us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.200s 401.161us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.200s 401.161us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.110s 152.618us 1 1 100.00
rstmgr_csr_rw 0.830s 68.911us 1 1 100.00
rstmgr_csr_aliasing 1.750s 164.066us 1 1 100.00
rstmgr_same_csr_outstanding 1.060s 98.657us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.110s 152.618us 1 1 100.00
rstmgr_csr_rw 0.830s 68.911us 1 1 100.00
rstmgr_csr_aliasing 1.750s 164.066us 1 1 100.00
rstmgr_same_csr_outstanding 1.060s 98.657us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 24.820s 16816.217us 1 1 100.00
rstmgr_tl_intg_err 1.650s 453.535us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 24.820s 16816.217us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 24.820s 16816.217us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 1.650s 453.535us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 0.980s 160.317us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 5.780s 1974.551us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.560s 302.285us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 24.820s 16816.217us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.830s 68.911us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.830s 68.911us 1 1 100.00