Simulation Results: rv_timer

 
29/04/2026 15:30:23 DVSim: v1.33.0 sha: a64a82b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.40 %
  • code
  • 99.92 %
  • assert
  • 96.82 %
  • func
  • 86.47 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 99.69 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.580s 14.175us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.610s 14.252us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.570s 37.958us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.300s 428.983us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.670s 59.883us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.030s 174.609us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.570s 37.958us 1 1 100.00
rv_timer_csr_aliasing 0.670s 59.883us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.700s 614.230us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 3.300s 3074.487us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 5.980s 9580.795us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 5.980s 9580.795us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 6.070s 7730.156us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.600s 39.243us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.580s 15.679us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 2.010s 284.328us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 2.010s 284.328us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.610s 14.252us 1 1 100.00
rv_timer_csr_rw 0.570s 37.958us 1 1 100.00
rv_timer_csr_aliasing 0.670s 59.883us 1 1 100.00
rv_timer_same_csr_outstanding 0.630s 24.777us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.610s 14.252us 1 1 100.00
rv_timer_csr_rw 0.570s 37.958us 1 1 100.00
rv_timer_csr_aliasing 0.670s 59.883us 1 1 100.00
rv_timer_same_csr_outstanding 0.630s 24.777us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.910s 995.873us 1 1 100.00
rv_timer_tl_intg_err 0.970s 1059.315us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 0.970s 1059.315us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.760s 119.113us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.640s 47.830us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
rv_timer_stress_all_with_rand_reset 1.510s 90.334us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == *
rv_timer_min 85005950175399560700163539446587234313273132414696528119130371217903048976806 75
UVM_INFO @ 119112501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 27298377813402540970514563462780551424558563278556791914621657310294226833016 75
UVM_INFO @ 614229724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*])
rv_timer_max 65247461206625272844508556416031022716066221105533855862019274695404424873180 75
UVM_INFO @ 47830107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1170) [rv_timer_common_vseq] Check failed (vseq_done)
rv_timer_stress_all_with_rand_reset 99402375100511148100754389034782289976246714033245291195108773498360880798658 81
UVM_INFO @ 90333538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---