Simulation Results: spi_device/1r1w

 
29/04/2026 15:30:23 DVSim: v1.33.0 sha: a64a82b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.88 %
  • code
  • 93.30 %
  • assert
  • 94.64 %
  • func
  • 69.69 %
  • line
  • 99.07 %
  • branch
  • 98.30 %
  • cond
  • 96.21 %
  • toggle
  • 83.54 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
92.31%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 9.160s 2499.665us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 0.880s 17.460us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.280s 34.135us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 15.640s 356.902us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 10.940s 753.651us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 1.530s 42.973us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.280s 34.135us 1 1 100.00
spi_device_csr_aliasing 10.940s 753.651us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.760s 32.062us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.400s 44.734us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.690s 57.646us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.740s 16.756us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.860s 3.837us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 2.370s 197.133us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 2.370s 197.133us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 12.040s 12881.560us 1 1 100.00
spi_device_tpm_sts_read 0.930s 431.366us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 23.900s 30784.100us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 8.010s 1388.118us 1 1 100.00
spi_device_flash_all 82.830s 14044.422us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.020s 709.819us 1 1 100.00
spi_device_flash_all 82.830s 14044.422us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.020s 709.819us 1 1 100.00
spi_device_flash_all 82.830s 14044.422us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 82.830s 14044.422us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 3.800s 208.514us 1 1 100.00
spi_device_flash_all 82.830s 14044.422us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 3.800s 208.514us 1 1 100.00
spi_device_flash_all 82.830s 14044.422us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 3.800s 208.514us 1 1 100.00
spi_device_flash_all 82.830s 14044.422us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 3.800s 208.514us 1 1 100.00
spi_device_flash_all 82.830s 14044.422us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 3.800s 208.514us 1 1 100.00
spi_device_flash_all 82.830s 14044.422us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 6.950s 2018.690us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 12.910s 934.872us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 12.910s 934.872us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 12.910s 934.872us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 27.010s 12912.955us 1 1 100.00
spi_device_read_buffer_direct 2.840s 148.613us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 12.910s 934.872us 1 1 100.00
spi_device_flash_all 82.830s 14044.422us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 82.830s 14044.422us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 82.830s 14044.422us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 2.840s 512.959us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 2.840s 512.959us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 9.160s 2499.665us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 39.340s 29040.290us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 268.900s 336486.760us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.670s 13.856us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.810s 18.767us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 2.350s 221.621us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 2.350s 221.621us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 0.880s 17.460us 1 1 100.00
spi_device_csr_rw 1.280s 34.135us 1 1 100.00
spi_device_csr_aliasing 10.940s 753.651us 1 1 100.00
spi_device_same_csr_outstanding 2.230s 210.051us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 0.880s 17.460us 1 1 100.00
spi_device_csr_rw 1.280s 34.135us 1 1 100.00
spi_device_csr_aliasing 10.940s 753.651us 1 1 100.00
spi_device_same_csr_outstanding 2.230s 210.051us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.220s 161.570us 1 1 100.00
spi_device_tl_intg_err 12.410s 999.536us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 12.410s 999.536us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 73.050s 52798.935us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*])
spi_device_mem_parity 45893127773323655638780709506671713825705357603024925227576121553153431811571 76
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 9955903 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 9955903 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[917])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*])
spi_device_ram_cfg 75870199145701002356803416938403558606111679744219814731325630863797813838384 76
UVM_ERROR @ 1175723 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x51ebde [10100011110101111011110] vs 0x0 [0])
UVM_ERROR @ 1229723 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x7798dc [11101111001100011011100] vs 0x0 [0])
UVM_ERROR @ 1296723 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x8630a2 [100001100011000010100010] vs 0x0 [0])
UVM_ERROR @ 1305723 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x351be0 [1101010001101111100000] vs 0x0 [0])