Simulation Results: spi_host

 
29/04/2026 15:30:23 DVSim: v1.33.0 sha: a64a82b json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.56 %
  • code
  • 94.90 %
  • assert
  • 94.13 %
  • func
  • 88.66 %
  • block
  • 96.78 %
  • line
  • 98.54 %
  • branch
  • 93.05 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 2.000s 257.460us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 44.424us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 2.000s 80.957us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 57.622us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 58.848us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 71.310us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 2.000s 80.957us 1 1 100.00
spi_host_csr_aliasing 1.000s 58.848us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 65.908us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 19.289us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 1.000s 48.276us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 2.000s 47.748us 1 1 100.00
spi_host_error_cmd 2.000s 46.308us 1 1 100.00
spi_host_event 38.000s 10901.938us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 1.000s 171.984us 1 1 100.00
speed 1 1 100.00
spi_host_speed 1.000s 171.984us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 1.000s 171.984us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 7.000s 330.389us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 143.842us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 1.000s 171.984us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 1.000s 171.984us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 2.000s 257.460us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 2.000s 257.460us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 18.000s 1355.885us 1 1 100.00
spien 1 1 100.00
spi_host_spien 3.000s 411.186us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 32.000s 2623.912us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 12.000s 1780.566us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 2.000s 47.748us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 35.533us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 2.000s 57.513us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 3.000s 163.275us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 3.000s 163.275us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 44.424us 1 1 100.00
spi_host_csr_rw 2.000s 80.957us 1 1 100.00
spi_host_csr_aliasing 1.000s 58.848us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 28.888us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 44.424us 1 1 100.00
spi_host_csr_rw 2.000s 80.957us 1 1 100.00
spi_host_csr_aliasing 1.000s 58.848us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 28.888us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 2.000s 252.897us 1 1 100.00
spi_host_sec_cm 1.000s 65.748us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 252.897us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
spi_host_upper_range_clkdiv 118.000s 200000.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
spi_host_upper_range_clkdiv 106573394249500258647449529504251158804641226086126531512951236323558247227951 129
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---