Simulation Results: sram_ctrl/main

 
29/04/2026 15:30:23 DVSim: v1.33.0 sha: a64a82b json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.43 %
  • code
  • 96.83 %
  • assert
  • 96.46 %
  • func
  • 93.00 %
  • block
  • 96.15 %
  • line
  • 96.88 %
  • branch
  • 94.33 %
  • toggle
  • 96.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 4.000s 674.639us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 14.751us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 49.261us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 31.353us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 62.928us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 4.000s 724.589us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 49.261us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 62.928us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 88.000s 2715.843us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 107.000s 5513.302us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 38.000s 7759.370us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 210.000s 11239.745us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 140.000s 39585.803us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 59.000s 94495.587us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 21.000s 7279.514us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 30.000s 22469.432us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 6.000s 2691.866us 1 1 100.00
sram_ctrl_partial_access_b2b 200.000s 14328.594us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 4.000s 1395.787us 1 1 100.00
sram_ctrl_throughput_w_partial_write 4.000s 673.604us 1 1 100.00
sram_ctrl_throughput_w_readback 5.000s 708.452us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 15.000s 3226.490us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.000s 693.045us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 148.000s 8704.687us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 21.489us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 5.000s 36.761us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 5.000s 36.761us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 14.751us 1 1 100.00
sram_ctrl_csr_rw 1.000s 49.261us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 62.928us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 16.205us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 14.751us 1 1 100.00
sram_ctrl_csr_rw 1.000s 49.261us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 62.928us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 16.205us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 13.000s 9462.588us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 3253.060us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 1450.862us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 3253.060us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 1450.862us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 15.000s 3226.490us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 15.000s 3226.490us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 49.261us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 30.000s 22469.432us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 30.000s 22469.432us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 30.000s 22469.432us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 21.000s 7279.514us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.000s 2671.870us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 13.000s 9462.588us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 4.000s 1365.313us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 674.639us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 674.639us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 30.000s 22469.432us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 3253.060us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 21.000s 7279.514us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 3253.060us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 3253.060us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 4.000s 674.639us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 3253.060us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 39.000s 8377.740us 1 1 100.00