Simulation Results: sram_ctrl/ret

 
29/04/2026 15:30:23 DVSim: v1.33.0 sha: a64a82b json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 90.91 %
  • code
  • 82.84 %
  • assert
  • 96.29 %
  • func
  • 93.60 %
  • block
  • 93.05 %
  • line
  • 94.14 %
  • branch
  • 88.26 %
  • toggle
  • 82.28 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 3.000s 399.004us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 41.283us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 13.781us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 30.669us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 15.907us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 74.966us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 13.781us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 15.907us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 4.000s 240.742us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 4.000s 71.470us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 7.000s 1883.128us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 200.000s 3883.069us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 6.000s 923.438us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 15.000s 2335.302us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 3.000s 189.742us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 11.000s 1916.763us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 57.736us 1 1 100.00
sram_ctrl_partial_access_b2b 94.000s 5140.802us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 1.000s 210.741us 1 1 100.00
sram_ctrl_throughput_w_partial_write 1.000s 120.741us 1 1 100.00
sram_ctrl_throughput_w_readback 1.000s 155.449us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 11.000s 859.402us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 79.564us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 36.000s 15192.274us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 34.356us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 89.804us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 89.804us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 41.283us 1 1 100.00
sram_ctrl_csr_rw 1.000s 13.781us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 15.907us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 29.128us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 41.283us 1 1 100.00
sram_ctrl_csr_rw 1.000s 13.781us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 15.907us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 29.128us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 403.302us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 5.000s 4756.114us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 952.530us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 5.000s 4756.114us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 952.530us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 11.000s 859.402us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 11.000s 859.402us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 13.781us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 11.000s 1916.763us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 11.000s 1916.763us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 11.000s 1916.763us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 3.000s 189.742us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 2.000s 65.330us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 403.302us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 1.000s 631.110us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 399.004us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 399.004us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 11.000s 1916.763us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 5.000s 4756.114us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 3.000s 189.742us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 5.000s 4756.114us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 5.000s 4756.114us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 3.000s 399.004us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 5.000s 4756.114us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 35.000s 1512.349us 1 1 100.00