Simulation Results: sysrst_ctrl

 
29/04/2026 15:30:23 DVSim: v1.33.0 sha: a64a82b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.26 %
  • code
  • 93.73 %
  • assert
  • 94.92 %
  • func
  • 61.13 %
  • line
  • 97.88 %
  • branch
  • 97.81 %
  • cond
  • 95.38 %
  • toggle
  • 100.00 %
  • FSM
  • 77.56 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 4.460s 2112.567us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 5.250s 2444.579us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 1.350s 2266.316us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 3.120s 2549.818us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 2.070s 6157.893us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 2.640s 2031.148us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 12.030s 3942.664us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 6.250s 2599.567us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 3.480s 2111.857us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 2.640s 2031.148us 1 1 100.00
sysrst_ctrl_csr_aliasing 6.250s 2599.567us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 125.080s 150152.335us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 12.920s 26108.673us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 1.340s 3659.296us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 3.250s 2705.811us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 5.600s 2511.933us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 4.610s 2035.967us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 1.720s 2586.161us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 5.630s 2614.482us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 145.000s 2822040.406us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 22.330s 42382.067us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 87.770s 419733.430us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 4.940s 2009.299us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 4.280s 2010.303us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 5.260s 2022.499us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 5.260s 2022.499us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 2.070s 6157.893us 1 1 100.00
sysrst_ctrl_csr_rw 2.640s 2031.148us 1 1 100.00
sysrst_ctrl_csr_aliasing 6.250s 2599.567us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 9.900s 9721.384us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 2.070s 6157.893us 1 1 100.00
sysrst_ctrl_csr_rw 2.640s 2031.148us 1 1 100.00
sysrst_ctrl_csr_aliasing 6.250s 2599.567us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 9.900s 9721.384us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 82.260s 42010.653us 1 1 100.00
sysrst_ctrl_tl_intg_err 49.070s 22205.771us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 49.070s 22205.771us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 12.130s 6290.579us 1 1 100.00