Simulation Results: uart

 
29/04/2026 15:30:23 DVSim: v1.33.0 sha: a64a82b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.83 %
  • code
  • 96.74 %
  • assert
  • 97.12 %
  • func
  • 51.62 %
  • line
  • 99.48 %
  • branch
  • 98.14 %
  • cond
  • 97.78 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 18.320s 5489.409us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.790s 35.889us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.570s 50.747us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.670s 381.120us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.790s 20.049us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.750s 104.688us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.570s 50.747us 1 1 100.00
uart_csr_aliasing 0.790s 20.049us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 35.740s 31310.555us 1 1 100.00
parity 2 2 100.00
uart_smoke 18.320s 5489.409us 1 1 100.00
uart_tx_rx 35.740s 31310.555us 1 1 100.00
parity_error 2 2 100.00
uart_intr 30.720s 52357.814us 1 1 100.00
uart_rx_parity_err 18.290s 53386.077us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 35.740s 31310.555us 1 1 100.00
uart_intr 30.720s 52357.814us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 104.400s 114463.039us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 47.270s 39876.008us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 47.700s 176053.552us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 30.720s 52357.814us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 30.720s 52357.814us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 30.720s 52357.814us 1 1 100.00
perf 1 1 100.00
uart_perf 189.030s 22775.912us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 8.870s 13459.497us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 8.870s 13459.497us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 1.760s 2028.292us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 1.480s 3822.327us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 2.290s 973.540us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 6.100s 5731.925us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 111.320s 39032.632us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 32.430s 164388.099us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.610s 10.921us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.570s 81.491us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.900s 184.330us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.900s 184.330us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.790s 35.889us 1 1 100.00
uart_csr_rw 0.570s 50.747us 1 1 100.00
uart_csr_aliasing 0.790s 20.049us 1 1 100.00
uart_same_csr_outstanding 0.840s 87.435us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.790s 35.889us 1 1 100.00
uart_csr_rw 0.570s 50.747us 1 1 100.00
uart_csr_aliasing 0.790s 20.049us 1 1 100.00
uart_same_csr_outstanding 0.840s 87.435us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.900s 260.694us 1 1 100.00
uart_tl_intg_err 1.200s 310.092us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.200s 310.092us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 31.080s 4863.149us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: *
uart_noise_filter 101604261263147813992393487130680688225792193544255389973180695797856349959977 74
UVM_ERROR @ 67506118 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 67536421 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 239 [0xef]) reg name: uart_reg_block.rdata
UVM_ERROR @ 89627308 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 100809115 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0