Simulation Results: adc_ctrl

 
30/04/2026 15:30:31 DVSim: v1.33.0 sha: c776b8b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 65.43 %
  • code
  • 92.32 %
  • assert
  • 90.92 %
  • func
  • 13.04 %
  • line
  • 98.06 %
  • branch
  • 96.35 %
  • cond
  • 86.35 %
  • toggle
  • 99.76 %
  • FSM
  • 81.08 %
Validation stages
V1
100.00%
V2
52.63%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 9.490s 5710.608us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.210s 1043.765us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.040s 539.927us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 12.780s 29666.297us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 2.730s 1021.316us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.480s 389.149us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.040s 539.927us 1 1 100.00
adc_ctrl_csr_aliasing 2.730s 1021.316us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 0 1 0.00
adc_ctrl_filters_polled 1.340s 399.250us 0 1 0.00
filters_polled_fixed 0 1 0.00
adc_ctrl_filters_polled_fixed 1.170s 312.794us 0 1 0.00
filters_interrupt 0 1 0.00
adc_ctrl_filters_interrupt 1.010s 412.082us 0 1 0.00
filters_interrupt_fixed 0 1 0.00
adc_ctrl_filters_interrupt_fixed 0.670s 391.817us 0 1 0.00
filters_wakeup 0 1 0.00
adc_ctrl_filters_wakeup 1.520s 522.185us 0 1 0.00
filters_wakeup_fixed 0 1 0.00
adc_ctrl_filters_wakeup_fixed 0.970s 310.513us 0 1 0.00
filters_both 0 1 0.00
adc_ctrl_filters_both 1.480s 342.697us 0 1 0.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 1.970s 424.659us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 2.750s 4471.494us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 14.230s 31457.967us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 181.810s 98923.911us 1 1 100.00
stress_all 0 1 0.00
adc_ctrl_stress_all 0.940s 714.988us 0 1 0.00
alert_test 1 1 100.00
adc_ctrl_alert_test 0.790s 478.225us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 1.030s 479.495us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 1.710s 671.805us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 1.710s 671.805us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.210s 1043.765us 1 1 100.00
adc_ctrl_csr_rw 1.040s 539.927us 1 1 100.00
adc_ctrl_csr_aliasing 2.730s 1021.316us 1 1 100.00
adc_ctrl_same_csr_outstanding 4.040s 5330.061us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.210s 1043.765us 1 1 100.00
adc_ctrl_csr_rw 1.040s 539.927us 1 1 100.00
adc_ctrl_csr_aliasing 2.730s 1021.316us 1 1 100.00
adc_ctrl_same_csr_outstanding 4.040s 5330.061us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 11.030s 7097.069us 1 1 100.00
adc_ctrl_tl_intg_err 3.450s 4532.990us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 3.450s 4532.990us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
adc_ctrl_stress_all_with_rand_reset 1.170s 1572.627us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [*, *]
adc_ctrl_filters_polled 18315865679166662175992283803718594327128535942730977668802095394055265590184 389
UVM_INFO @ 399249944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 79707077015714176822816993195695599275895626246663093098617126192553219197188 389
UVM_INFO @ 312793993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 75601374590474664251274324492616249494104953867065802809065809058277835413126 389
UVM_INFO @ 412082230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 31430896526665498793985032220284361621531380417831353482214080294003429776238 389
UVM_INFO @ 391817398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 110270550483485401277736675402755978874662393492830511514776289196908471925323 389
UVM_INFO @ 522184766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 15418779904701094403200641339239329486631166838328497737827271016303066313302 389
UVM_INFO @ 310512581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 77952148532709457833335365341616988002433087140882434460229010180342505540122 389
UVM_INFO @ 424659007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 55902968094298133330233077531527647776326187748628137362388627424754567009181 389
UVM_INFO @ 342696561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 24187147282893318226796681957210325898090565533363441684592033694094170021480 390
UVM_INFO @ 714987558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---