Simulation Results: aes/masked

 
30/04/2026 15:30:31 DVSim: v1.33.0 sha: c776b8b json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.43 %
  • code
  • 95.16 %
  • assert
  • 98.29 %
  • func
  • 68.83 %
  • block
  • 95.81 %
  • line
  • 97.53 %
  • branch
  • 89.58 %
  • toggle
  • 98.05 %
  • FSM
  • 95.48 %
Validation stages
V1
100.00%
V2
100.00%
V2S
94.44%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 5.000s 328.687us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 79.900us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 59.168us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 103.942us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 3.000s 365.554us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 4.000s 168.303us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 67.832us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 103.942us 1 1 100.00
aes_csr_aliasing 4.000s 168.303us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 79.900us 1 1 100.00
aes_config_error 2.000s 156.763us 1 1 100.00
aes_stress 4.000s 174.750us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 79.900us 1 1 100.00
aes_config_error 2.000s 156.763us 1 1 100.00
aes_stress 4.000s 174.750us 1 1 100.00
back2back 2 2 100.00
aes_stress 4.000s 174.750us 1 1 100.00
aes_b2b 8.000s 523.789us 1 1 100.00
backpressure 1 1 100.00
aes_stress 4.000s 174.750us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 79.900us 1 1 100.00
aes_config_error 2.000s 156.763us 1 1 100.00
aes_stress 4.000s 174.750us 1 1 100.00
aes_alert_reset 18.000s 1172.053us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 67.068us 1 1 100.00
aes_config_error 2.000s 156.763us 1 1 100.00
aes_alert_reset 18.000s 1172.053us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 97.797us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 8.000s 334.496us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 8.000s 2412.717us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 18.000s 1172.053us 1 1 100.00
stress 1 1 100.00
aes_stress 4.000s 174.750us 1 1 100.00
sideload 2 2 100.00
aes_stress 4.000s 174.750us 1 1 100.00
aes_sideload 2.000s 148.337us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 4.000s 76.900us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 13.000s 538.166us 1 1 100.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 5.000s 204.522us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 3.000s 143.503us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 527.119us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 527.119us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 59.168us 1 1 100.00
aes_csr_rw 2.000s 103.942us 1 1 100.00
aes_csr_aliasing 4.000s 168.303us 1 1 100.00
aes_same_csr_outstanding 2.000s 159.668us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 59.168us 1 1 100.00
aes_csr_rw 2.000s 103.942us 1 1 100.00
aes_csr_aliasing 4.000s 168.303us 1 1 100.00
aes_same_csr_outstanding 2.000s 159.668us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 4.000s 177.230us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 18.000s 10035.471us 0 1 0.00
aes_control_fi 2.000s 54.409us 1 1 100.00
aes_cipher_fi 3.000s 63.505us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 184.376us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 184.376us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 184.376us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 184.376us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 155.383us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 6.000s 1967.570us 1 1 100.00
aes_tl_intg_err 3.000s 675.615us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 675.615us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 18.000s 1172.053us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 184.376us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 184.376us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 3.000s 79.900us 1 1 100.00
aes_stress 4.000s 174.750us 1 1 100.00
aes_alert_reset 18.000s 1172.053us 1 1 100.00
aes_core_fi 2.000s 277.628us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 5.000s 204.522us 1 1 100.00
aes_config_error 2.000s 156.763us 1 1 100.00
aes_stress 4.000s 174.750us 1 1 100.00
aes_core_fi 2.000s 277.628us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 184.376us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 72.297us 1 1 100.00
aes_stress 4.000s 174.750us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 4.000s 174.750us 1 1 100.00
aes_sideload 2.000s 148.337us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 72.297us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 72.297us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 72.297us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 72.297us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 72.297us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 4.000s 174.750us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 4.000s 174.750us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 18.000s 10035.471us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 18.000s 10035.471us 0 1 0.00
aes_control_fi 2.000s 54.409us 1 1 100.00
aes_cipher_fi 3.000s 63.505us 1 1 100.00
aes_ctr_fi 3.000s 54.399us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 18.000s 10035.471us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 18.000s 10035.471us 0 1 0.00
aes_control_fi 2.000s 54.409us 1 1 100.00
aes_cipher_fi 3.000s 63.505us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 3.000s 63.505us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 18.000s 10035.471us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 18.000s 10035.471us 0 1 0.00
aes_control_fi 2.000s 54.409us 1 1 100.00
aes_ctr_fi 3.000s 54.399us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 18.000s 10035.471us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 18.000s 10035.471us 0 1 0.00
aes_control_fi 2.000s 54.409us 1 1 100.00
aes_cipher_fi 3.000s 63.505us 1 1 100.00
aes_ctr_fi 3.000s 54.399us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 18.000s 1172.053us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 18.000s 10035.471us 0 1 0.00
aes_control_fi 2.000s 54.409us 1 1 100.00
aes_cipher_fi 3.000s 63.505us 1 1 100.00
aes_ctr_fi 3.000s 54.399us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 18.000s 10035.471us 0 1 0.00
aes_control_fi 2.000s 54.409us 1 1 100.00
aes_cipher_fi 3.000s 63.505us 1 1 100.00
aes_ctr_fi 3.000s 54.399us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 18.000s 10035.471us 0 1 0.00
aes_control_fi 2.000s 54.409us 1 1 100.00
aes_ctr_fi 3.000s 54.399us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_fi 18.000s 10035.471us 0 1 0.00
aes_ghash_fi 2.000s 47.655us 1 1 100.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 18.000s 10035.471us 0 1 0.00
aes_control_fi 2.000s 54.409us 1 1 100.00
aes_cipher_fi 3.000s 63.505us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 22.000s 1531.389us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:454) [aes_fi_vseq] wait timeout occurred!
aes_fi 5505546206206349205354812919666937445682778980259064013183357797502195347061 683
UVM_INFO @ 10035470616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
aes_stress_all_with_rand_reset 18287716401876155994596587077928149595320192275668825417324170138119319998450 225
UVM_INFO @ 1531389188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---