Simulation Results: aes/unmasked

 
30/04/2026 15:30:31 DVSim: v1.33.0 sha: c776b8b json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 85.30 %
  • code
  • 91.32 %
  • assert
  • 97.75 %
  • func
  • 66.82 %
  • block
  • 90.78 %
  • line
  • 93.14 %
  • branch
  • 83.37 %
  • toggle
  • 97.99 %
  • FSM
  • 90.78 %
Validation stages
V1
100.00%
V2
94.74%
V2S
77.78%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 183.591us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 111.598us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 99.829us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 50.149us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 6.000s 2445.899us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 4.000s 311.808us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 65.730us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 50.149us 1 1 100.00
aes_csr_aliasing 4.000s 311.808us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 111.598us 1 1 100.00
aes_config_error 3.000s 108.450us 1 1 100.00
aes_stress 3.000s 313.492us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 111.598us 1 1 100.00
aes_config_error 3.000s 108.450us 1 1 100.00
aes_stress 3.000s 313.492us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 313.492us 1 1 100.00
aes_b2b 3.000s 140.635us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 313.492us 1 1 100.00
multi_message 3 4 75.00
aes_smoke 2.000s 111.598us 1 1 100.00
aes_config_error 3.000s 108.450us 1 1 100.00
aes_stress 3.000s 313.492us 1 1 100.00
aes_alert_reset 20.000s 10017.230us 0 1 0.00
failure_test 2 3 66.67
aes_man_cfg_err 2.000s 75.697us 1 1 100.00
aes_config_error 3.000s 108.450us 1 1 100.00
aes_alert_reset 20.000s 10017.230us 0 1 0.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 116.419us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 391.380us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 4.000s 276.390us 1 1 100.00
reset_recovery 0 1 0.00
aes_alert_reset 20.000s 10017.230us 0 1 0.00
stress 1 1 100.00
aes_stress 3.000s 313.492us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 313.492us 1 1 100.00
aes_sideload 3.000s 814.049us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 91.263us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 6.000s 174.257us 1 1 100.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 2.000s 344.098us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 101.175us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 121.516us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 121.516us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 99.829us 1 1 100.00
aes_csr_rw 1.000s 50.149us 1 1 100.00
aes_csr_aliasing 4.000s 311.808us 1 1 100.00
aes_same_csr_outstanding 2.000s 73.198us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 99.829us 1 1 100.00
aes_csr_rw 1.000s 50.149us 1 1 100.00
aes_csr_aliasing 4.000s 311.808us 1 1 100.00
aes_same_csr_outstanding 2.000s 73.198us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 3.000s 704.627us 1 1 100.00
fault_inject 1 3 33.33
aes_fi 18.000s 10024.846us 0 1 0.00
aes_control_fi 2.000s 147.398us 1 1 100.00
aes_cipher_fi 33.000s 10004.065us 0 1 0.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 1.000s 111.593us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 1.000s 111.593us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 1.000s 111.593us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 1.000s 111.593us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 169.343us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 3.000s 467.499us 1 1 100.00
aes_tl_intg_err 3.000s 367.663us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 367.663us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
aes_alert_reset 20.000s 10017.230us 0 1 0.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 111.593us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 111.593us 1 1 100.00
sec_cm_main_config_sparse 2 4 50.00
aes_smoke 2.000s 111.598us 1 1 100.00
aes_stress 3.000s 313.492us 1 1 100.00
aes_alert_reset 20.000s 10017.230us 0 1 0.00
aes_core_fi 28.000s 10005.468us 0 1 0.00
sec_cm_gcm_config_sparse 3 4 75.00
aes_gcm_save_restore 2.000s 344.098us 1 1 100.00
aes_config_error 3.000s 108.450us 1 1 100.00
aes_stress 3.000s 313.492us 1 1 100.00
aes_core_fi 28.000s 10005.468us 0 1 0.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 111.593us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 1.000s 70.259us 1 1 100.00
aes_stress 3.000s 313.492us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 313.492us 1 1 100.00
aes_sideload 3.000s 814.049us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 1.000s 70.259us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 1.000s 70.259us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 1.000s 70.259us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 1.000s 70.259us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 1.000s 70.259us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 313.492us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 313.492us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 18.000s 10024.846us 0 1 0.00
sec_cm_main_fsm_redun 2 4 50.00
aes_fi 18.000s 10024.846us 0 1 0.00
aes_control_fi 2.000s 147.398us 1 1 100.00
aes_cipher_fi 33.000s 10004.065us 0 1 0.00
aes_ctr_fi 2.000s 67.046us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 18.000s 10024.846us 0 1 0.00
sec_cm_cipher_fsm_redun 1 3 33.33
aes_fi 18.000s 10024.846us 0 1 0.00
aes_control_fi 2.000s 147.398us 1 1 100.00
aes_cipher_fi 33.000s 10004.065us 0 1 0.00
sec_cm_cipher_ctr_redun 0 1 0.00
aes_cipher_fi 33.000s 10004.065us 0 1 0.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 18.000s 10024.846us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 18.000s 10024.846us 0 1 0.00
aes_control_fi 2.000s 147.398us 1 1 100.00
aes_ctr_fi 2.000s 67.046us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 18.000s 10024.846us 0 1 0.00
sec_cm_ctrl_sparse 2 4 50.00
aes_fi 18.000s 10024.846us 0 1 0.00
aes_control_fi 2.000s 147.398us 1 1 100.00
aes_cipher_fi 33.000s 10004.065us 0 1 0.00
aes_ctr_fi 2.000s 67.046us 1 1 100.00
sec_cm_main_fsm_global_esc 0 1 0.00
aes_alert_reset 20.000s 10017.230us 0 1 0.00
sec_cm_main_fsm_local_esc 2 4 50.00
aes_fi 18.000s 10024.846us 0 1 0.00
aes_control_fi 2.000s 147.398us 1 1 100.00
aes_cipher_fi 33.000s 10004.065us 0 1 0.00
aes_ctr_fi 2.000s 67.046us 1 1 100.00
sec_cm_cipher_fsm_local_esc 2 4 50.00
aes_fi 18.000s 10024.846us 0 1 0.00
aes_control_fi 2.000s 147.398us 1 1 100.00
aes_cipher_fi 33.000s 10004.065us 0 1 0.00
aes_ctr_fi 2.000s 67.046us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 18.000s 10024.846us 0 1 0.00
aes_control_fi 2.000s 147.398us 1 1 100.00
aes_ctr_fi 2.000s 67.046us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_fi 18.000s 10024.846us 0 1 0.00
aes_ghash_fi 1.000s 46.086us 1 1 100.00
sec_cm_data_reg_local_esc 1 3 33.33
aes_fi 18.000s 10024.846us 0 1 0.00
aes_control_fi 2.000s 147.398us 1 1 100.00
aes_cipher_fi 33.000s 10004.065us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 17.000s 928.607us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:454) [aes_alert_reset_vseq] wait timeout occurred!
aes_alert_reset 106518900193803377790272114092585973579042196730895661549235667957199077741884 438
UVM_INFO @ 10017230434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [aes_fi_vseq] wait timeout occurred!
aes_fi 116929225410110111733138985936166587192911739038117028755857341839670946736 575
UVM_INFO @ 10024845925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred!
aes_cipher_fi 86351465024914327685643560072567684146248306329673301293228826811193043338247 148
UVM_INFO @ 10004065280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [aes_core_fi_vseq] wait timeout occurred!
aes_core_fi 51452767562387362335571609912818434857450031035427481030975439524728868211628 139
UVM_INFO @ 10005468132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
aes_stress_all_with_rand_reset 8786649770701111658455872546882395134634319146622727959722652025327218536952 400
UVM_INFO @ 928606577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---