Simulation Results

Simulation Results: chip

30/04/2026 15:30:31 DVSim: v1.33.0 sha: c776b8b json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
76.16 %

code
84.50 %

assert
97.37 %

func
46.61 %

line
93.97 %

branch
92.24 %

cond
87.87 %

toggle
91.28 %

FSM
57.14 %

Validation stages

V1		100.00%
V2		78.06%
V2S		50.00%
V3		65.38%
unmapped		80.00%

18/18 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_example_tests				4	4	100.00
	chip_sw_example_flash	183.230s	2768.368us	1	1	100.00
	chip_sw_example_rom	83.950s	2639.619us	1	1	100.00
	chip_sw_example_manufacturer	166.360s	2876.979us	1	1	100.00
	chip_sw_example_concurrency	137.220s	2279.678us	1	1	100.00
csr_hw_reset				1	1	100.00
	chip_csr_hw_reset	169.870s	4644.368us	1	1	100.00
csr_rw				1	1	100.00
	chip_csr_rw	389.690s	5595.055us	1	1	100.00
csr_bit_bash				1	1	100.00
	chip_csr_bit_bash	339.330s	4948.770us	1	1	100.00
csr_aliasing				1	1	100.00
	chip_csr_aliasing	4720.480s	37633.277us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	chip_csr_mem_rw_with_rand_reset	371.960s	5568.748us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	chip_csr_aliasing	4720.480s	37633.277us	1	1	100.00
	chip_csr_rw	389.690s	5595.055us	1	1	100.00
xbar_smoke				1	1	100.00
	xbar_smoke	5.830s	200.159us	1	1	100.00
chip_sw_gpio_out				1	1	100.00
	chip_sw_gpio	295.450s	3804.860us	1	1	100.00
chip_sw_gpio_in				1	1	100.00
	chip_sw_gpio	295.450s	3804.860us	1	1	100.00
chip_sw_gpio_irq				1	1	100.00
	chip_sw_gpio	295.450s	3804.860us	1	1	100.00
chip_sw_uart_tx_rx				1	1	100.00
	chip_sw_uart_tx_rx	401.780s	4603.665us	1	1	100.00
chip_sw_uart_rx_overflow				4	4	100.00
	chip_sw_uart_tx_rx	401.780s	4603.665us	1	1	100.00
	chip_sw_uart_tx_rx_idx1	374.260s	4868.706us	1	1	100.00
	chip_sw_uart_tx_rx_idx2	316.490s	3695.341us	1	1	100.00
	chip_sw_uart_tx_rx_idx3	363.430s	4450.339us	1	1	100.00
chip_sw_uart_baud_rate				1	1	100.00
	chip_sw_uart_rand_baudrate	1025.960s	8501.672us	1	1	100.00
chip_sw_uart_tx_rx_alt_clk_freq				2	2	100.00
	chip_sw_uart_tx_rx_alt_clk_freq	385.520s	4658.803us	1	1	100.00
	chip_sw_uart_tx_rx_alt_clk_freq_low_speed	1080.280s	13770.171us	1	1	100.00

217/278 passed

78.06 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_pin_mux				1	1	100.00
	chip_padctrl_attributes	194.790s	5360.752us	1	1	100.00
chip_padctrl_attributes				1	1	100.00
	chip_padctrl_attributes	194.790s	5360.752us	1	1	100.00
chip_sw_sleep_pin_mio_dio_val				0	1	0.00
	chip_sw_sleep_pin_mio_dio_val	221.710s	3158.035us	0	1	0.00
chip_sw_sleep_pin_wake				1	1	100.00
	chip_sw_sleep_pin_wake	161.980s	3503.464us	1	1	100.00
chip_sw_sleep_pin_retention				1	1	100.00
	chip_sw_sleep_pin_retention	195.380s	3173.044us	1	1	100.00
chip_sw_tap_strap_sampling				4	4	100.00
	chip_tap_straps_dev	93.370s	2402.723us	1	1	100.00
	chip_tap_straps_testunlock0	347.500s	7191.606us	1	1	100.00
	chip_tap_straps_rma	196.130s	4052.433us	1	1	100.00
	chip_tap_straps_prod	90.580s	2828.798us	1	1	100.00
chip_sw_pattgen_ios				1	1	100.00
	chip_sw_pattgen_ios	136.940s	2909.965us	1	1	100.00
chip_sw_sleep_pwm_pulses				1	1	100.00
	chip_sw_sleep_pwm_pulses	771.170s	9081.039us	1	1	100.00
chip_sw_data_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	461.680s	5370.845us	1	1	100.00
chip_sw_instruction_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	461.680s	5370.845us	1	1	100.00
chip_sw_ast_clk_outputs				1	1	100.00
	chip_sw_ast_clk_outputs	697.240s	8651.907us	1	1	100.00
chip_sw_ast_clk_rst_inputs				0	1	0.00
	chip_sw_ast_clk_rst_inputs	672.360s	9006.911us	0	1	0.00
chip_sw_ast_sys_clk_jitter				10	10	100.00
	chip_sw_flash_ctrl_ops_jitter_en	334.960s	4685.486us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	587.930s	6054.996us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3565.720s	19561.179us	1	1	100.00
	chip_sw_aes_enc_jitter_en	194.840s	2914.690us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	764.900s	7960.148us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	170.800s	3133.476us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	745.220s	8100.176us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	202.330s	3832.207us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	312.130s	4095.897us	1	1	100.00
	chip_sw_clkmgr_jitter	163.390s	3359.635us	1	1	100.00
chip_sw_ast_usb_clk_calib				1	1	100.00
	chip_sw_usb_ast_clk_calib	168.250s	2689.569us	1	1	100.00
chip_sw_sensor_ctrl_ast_alerts				2	2	100.00
	chip_sw_sensor_ctrl_alert	474.960s	8553.883us	1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	244.970s	5870.716us	1	1	100.00
chip_sw_sensor_ctrl_ast_status				1	1	100.00
	chip_sw_sensor_ctrl_status	120.720s	2398.102us	1	1	100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup				1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	244.970s	5870.716us	1	1	100.00
chip_sw_smoketest				17	17	100.00
	chip_sw_flash_scrambling_smoketest	175.860s	2922.649us	1	1	100.00
	chip_sw_aes_smoketest	160.810s	3281.992us	1	1	100.00
	chip_sw_aon_timer_smoketest	217.320s	4009.412us	1	1	100.00
	chip_sw_clkmgr_smoketest	134.920s	2676.856us	1	1	100.00
	chip_sw_csrng_smoketest	180.380s	2495.060us	1	1	100.00
	chip_sw_entropy_src_smoketest	639.780s	5771.228us	1	1	100.00
	chip_sw_gpio_smoketest	206.720s	3155.434us	1	1	100.00
	chip_sw_hmac_smoketest	202.320s	3084.085us	1	1	100.00
	chip_sw_kmac_smoketest	213.490s	3483.458us	1	1	100.00
	chip_sw_otbn_smoketest	1281.290s	9920.544us	1	1	100.00
	chip_sw_pwrmgr_smoketest	268.530s	5215.823us	1	1	100.00
	chip_sw_pwrmgr_usbdev_smoketest	269.000s	6156.851us	1	1	100.00
	chip_sw_rv_plic_smoketest	132.030s	3022.838us	1	1	100.00
	chip_sw_rv_timer_smoketest	171.330s	3017.568us	1	1	100.00
	chip_sw_rstmgr_smoketest	157.160s	2735.728us	1	1	100.00
	chip_sw_sram_ctrl_smoketest	170.920s	3184.889us	1	1	100.00
	chip_sw_uart_smoketest	132.450s	2317.123us	1	1	100.00
chip_sw_otp_smoketest				1	1	100.00
	chip_sw_otp_ctrl_smoketest	185.960s	3148.952us	1	1	100.00
chip_sw_rom_functests				0	1	0.00
	rom_keymgr_functest	347.310s	4930.483us	0	1	0.00
chip_sw_boot				1	1	100.00
	chip_sw_uart_tx_rx_bootstrap	7674.390s	62739.810us	1	1	100.00
chip_sw_secure_boot				1	1	100.00
	rom_e2e_smoke	3213.050s	17055.974us	1	1	100.00
chip_sw_rom_raw_unlock				0	1	0.00
	rom_raw_unlock	41.020s	0.000us	0	1	0.00
chip_sw_power_idle_load				0	1	0.00
	chip_sw_power_idle_load	216.510s	3293.733us	0	1	0.00
chip_sw_power_sleep_load				0	1	0.00
	chip_sw_power_sleep_load	162.570s	2922.502us	0	1	0.00
chip_sw_exit_test_unlocked_bootstrap				1	1	100.00
	chip_sw_exit_test_unlocked_bootstrap	7127.180s	55291.268us	1	1	100.00
chip_sw_inject_scramble_seed				1	1	100.00
	chip_sw_inject_scramble_seed	7835.380s	57686.781us	1	1	100.00
tl_d_oob_addr_access				0	1	0.00
	chip_tl_errors	60.740s	1909.755us	0	1	0.00
tl_d_illegal_access				0	1	0.00
	chip_tl_errors	60.740s	1909.755us	0	1	0.00
tl_d_outstanding_access				4	4	100.00
	chip_csr_aliasing	4720.480s	37633.277us	1	1	100.00
	chip_same_csr_outstanding	3032.120s	30974.751us	1	1	100.00
	chip_csr_hw_reset	169.870s	4644.368us	1	1	100.00
	chip_csr_rw	389.690s	5595.055us	1	1	100.00
tl_d_partial_access				4	4	100.00
	chip_csr_aliasing	4720.480s	37633.277us	1	1	100.00
	chip_same_csr_outstanding	3032.120s	30974.751us	1	1	100.00
	chip_csr_hw_reset	169.870s	4644.368us	1	1	100.00
	chip_csr_rw	389.690s	5595.055us	1	1	100.00
xbar_base_random_sequence				1	1	100.00
	xbar_random	35.300s	1804.496us	1	1	100.00
xbar_random_delay				6	6	100.00
	xbar_smoke_zero_delays	5.480s	54.219us	1	1	100.00
	xbar_smoke_large_delays	60.520s	9937.809us	1	1	100.00
	xbar_smoke_slow_rsp	50.330s	5600.502us	1	1	100.00
	xbar_random_zero_delays	9.180s	104.271us	1	1	100.00
	xbar_random_large_delays	263.980s	46401.160us	1	1	100.00
	xbar_random_slow_rsp	67.620s	7892.768us	1	1	100.00
xbar_unmapped_address				2	2	100.00
	xbar_unmapped_addr	31.060s	971.145us	1	1	100.00
	xbar_error_and_unmapped_addr	15.200s	193.793us	1	1	100.00
xbar_error_cases				2	2	100.00
	xbar_error_random	5.660s	63.777us	1	1	100.00
	xbar_error_and_unmapped_addr	15.200s	193.793us	1	1	100.00
xbar_all_access_same_device				2	2	100.00
	xbar_access_same_device	29.000s	808.063us	1	1	100.00
	xbar_access_same_device_slow_rsp	557.070s	61306.447us	1	1	100.00
xbar_all_hosts_use_same_source_id				1	1	100.00
	xbar_same_source	33.070s	1728.185us	1	1	100.00
xbar_stress_all				2	2	100.00
	xbar_stress_all	74.590s	1476.577us	1	1	100.00
	xbar_stress_all_with_error	173.400s	7591.074us	1	1	100.00
xbar_stress_with_reset				2	2	100.00
	xbar_stress_all_with_rand_reset	298.010s	3843.263us	1	1	100.00
	xbar_stress_all_with_reset_error	196.320s	3591.284us	1	1	100.00
rom_e2e_smoke				1	1	100.00
	rom_e2e_smoke	3213.050s	17055.974us	1	1	100.00
rom_e2e_shutdown_output				1	1	100.00
	rom_e2e_shutdown_output	2614.360s	30122.196us	1	1	100.00
rom_e2e_shutdown_exception_c				1	1	100.00
	rom_e2e_shutdown_exception_c	2870.470s	15241.608us	1	1	100.00
rom_e2e_boot_policy_valid				0	15	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	51.268s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_dev	29.049s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod	43.437s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	30.417s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_rma	29.527s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	124.545s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	59.660s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	52.489s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	51.726s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	44.220s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	125.948s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	112.010s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	102.184s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	63.172s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	86.301s	0.000us	0	1	0.00
rom_e2e_sigverify_always				0	15	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	17.320s	10.400us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_dev	17.760s	10.260us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod	17.900s	10.400us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	17.910s	10.260us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_rma	19.910s	10.300us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	17.010s	10.280us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	21.800s	10.180us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	17.430s	10.300us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	17.790s	10.120us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	16.470s	10.180us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	16.250s	10.320us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	16.220s	10.280us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	16.460s	10.180us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	16.460s	10.320us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	19.570s	10.200us	0	1	0.00
rom_e2e_asm_init				0	5	0.00
	rom_e2e_asm_init_test_unlocked0	169.297s	0.000us	0	1	0.00
	rom_e2e_asm_init_dev	11.897s	0.000us	0	1	0.00
	rom_e2e_asm_init_prod	77.656s	0.000us	0	1	0.00
	rom_e2e_asm_init_prod_end	69.951s	0.000us	0	1	0.00
	rom_e2e_asm_init_rma	66.357s	0.000us	0	1	0.00
rom_e2e_keymgr_init				1	3	33.33
	rom_e2e_keymgr_init_rom_ext_meas	3202.980s	17131.878us	0	1	0.00
	rom_e2e_keymgr_init_rom_ext_no_meas	3001.540s	16592.982us	0	1	0.00
	rom_e2e_keymgr_init_rom_ext_invalid_meas	5795.370s	28399.748us	1	1	100.00
rom_e2e_static_critical				1	1	100.00
	rom_e2e_static_critical	3221.800s	16104.130us	1	1	100.00
chip_sw_adc_ctrl_debug_cable_irq				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3272.030s	34386.077us	0	1	0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3272.030s	34386.077us	0	1	0.00
chip_sw_aes_enc				2	2	100.00
	chip_sw_aes_enc	184.170s	3497.690us	1	1	100.00
	chip_sw_aes_enc_jitter_en	194.840s	2914.690us	1	1	100.00
chip_sw_aes_entropy				1	1	100.00
	chip_sw_aes_entropy	231.370s	3724.167us	1	1	100.00
chip_sw_aes_idle				1	1	100.00
	chip_sw_aes_idle	150.930s	3107.908us	1	1	100.00
chip_sw_aes_sideload				1	1	100.00
	chip_sw_keymgr_sideload_aes	1280.390s	10017.096us	1	1	100.00
chip_sw_alert_handler_alerts				0	1	0.00
	chip_sw_alert_test	168.180s	2835.145us	0	1	0.00
chip_sw_alert_handler_escalations				1	1	100.00
	chip_sw_alert_handler_escalation	424.810s	6030.923us	1	1	100.00
chip_sw_all_escalation_resets				1	1	100.00
	chip_sw_all_escalation_resets	428.440s	6362.231us	1	1	100.00
chip_sw_alert_handler_irqs				3	3	100.00
	chip_plic_all_irqs_0	566.460s	5550.430us	1	1	100.00
	chip_plic_all_irqs_10	238.160s	3238.412us	1	1	100.00
	chip_plic_all_irqs_20	359.690s	4606.859us	1	1	100.00
chip_sw_alert_handler_entropy				1	1	100.00
	chip_sw_alert_handler_entropy	192.730s	3960.376us	1	1	100.00
chip_sw_alert_handler_crashdump				1	1	100.00
	chip_sw_rstmgr_alert_info	1074.440s	11932.821us	1	1	100.00
chip_sw_alert_handler_ping_timeout				1	1	100.00
	chip_sw_alert_handler_ping_timeout	230.260s	4360.308us	1	1	100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_alerts	113.600s	2482.669us	0	1	0.00
chip_sw_alert_handler_lpg_sleep_mode_pings				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_pings	0.000s	0.000us	0	1	0.00
chip_sw_alert_handler_lpg_clock_off				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	993.550s	8220.837us	1	1	100.00
chip_sw_alert_handler_lpg_reset_toggle				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	868.710s	6853.544us	1	1	100.00
chip_sw_alert_handler_ping_ok				1	1	100.00
	chip_sw_alert_handler_ping_ok	801.200s	7807.690us	1	1	100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep				1	1	100.00
	chip_sw_alert_handler_reverse_ping_in_deep_sleep	8835.060s	255027.666us	1	1	100.00
chip_sw_aon_timer_wakeup_irq				1	1	100.00
	chip_sw_aon_timer_irq	266.630s	3518.375us	1	1	100.00
chip_sw_aon_timer_sleep_wakeup				1	1	100.00
	chip_sw_pwrmgr_smoketest	268.530s	5215.823us	1	1	100.00
chip_sw_aon_timer_wdog_bark_irq				1	1	100.00
	chip_sw_aon_timer_irq	266.630s	3518.375us	1	1	100.00
chip_sw_aon_timer_wdog_bite_reset				1	1	100.00
	chip_sw_aon_timer_wdog_bite_reset	471.950s	7172.708us	1	1	100.00
chip_sw_aon_timer_sleep_wdog_bite_reset				1	1	100.00
	chip_sw_aon_timer_wdog_bite_reset	471.950s	7172.708us	1	1	100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause				1	1	100.00
	chip_sw_aon_timer_sleep_wdog_sleep_pause	289.350s	6999.708us	1	1	100.00
chip_sw_aon_timer_wdog_lc_escalate				1	1	100.00
	chip_sw_aon_timer_wdog_lc_escalate	334.500s	5606.945us	1	1	100.00
chip_sw_clkmgr_idle_trans				4	4	100.00
	chip_sw_otbn_randomness	552.810s	5901.223us	1	1	100.00
	chip_sw_aes_idle	150.930s	3107.908us	1	1	100.00
	chip_sw_hmac_enc_idle	161.430s	2809.858us	1	1	100.00
	chip_sw_kmac_idle	169.100s	3399.789us	1	1	100.00
chip_sw_clkmgr_off_trans				4	4	100.00
	chip_sw_clkmgr_off_aes_trans	275.530s	3781.747us	1	1	100.00
	chip_sw_clkmgr_off_hmac_trans	295.300s	5410.555us	1	1	100.00
	chip_sw_clkmgr_off_kmac_trans	281.860s	3888.960us	1	1	100.00
	chip_sw_clkmgr_off_otbn_trans	267.640s	3961.193us	1	1	100.00
chip_sw_clkmgr_off_peri				1	1	100.00
	chip_sw_clkmgr_off_peri	636.640s	8877.693us	1	1	100.00
chip_sw_clkmgr_div				7	7	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	372.430s	3619.046us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	369.170s	4256.667us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	361.580s	4283.829us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	382.050s	5076.421us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	375.480s	3944.915us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	365.480s	5290.236us	1	1	100.00
	chip_sw_ast_clk_outputs	697.240s	8651.907us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_lc				1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	367.440s	7319.661us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_sw				2	2	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	361.580s	4283.829us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	382.050s	5076.421us	1	1	100.00
chip_sw_clkmgr_jitter				10	10	100.00
	chip_sw_flash_ctrl_ops_jitter_en	334.960s	4685.486us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	587.930s	6054.996us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3565.720s	19561.179us	1	1	100.00
	chip_sw_aes_enc_jitter_en	194.840s	2914.690us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	764.900s	7960.148us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	170.800s	3133.476us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	745.220s	8100.176us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	202.330s	3832.207us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	312.130s	4095.897us	1	1	100.00
	chip_sw_clkmgr_jitter	163.390s	3359.635us	1	1	100.00
chip_sw_clkmgr_extended_range				11	11	100.00
	chip_sw_clkmgr_jitter_reduced_freq	148.150s	3047.299us	1	1	100.00
	chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	409.670s	4783.292us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en_reduced_freq	653.390s	6907.449us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	4041.940s	25207.866us	1	1	100.00
	chip_sw_aes_enc_jitter_en_reduced_freq	144.210s	2973.415us	1	1	100.00
	chip_sw_hmac_enc_jitter_en_reduced_freq	135.700s	2831.625us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	1071.440s	11593.193us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	193.890s	2967.886us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	360.170s	5488.433us	1	1	100.00
	chip_sw_flash_init_reduced_freq	1283.910s	20475.185us	1	1	100.00
	chip_sw_csrng_edn_concurrency_reduced_freq	3556.510s	30386.695us	1	1	100.00
chip_sw_clkmgr_deep_sleep_frequency				1	1	100.00
	chip_sw_ast_clk_outputs	697.240s	8651.907us	1	1	100.00
chip_sw_clkmgr_sleep_frequency				1	1	100.00
	chip_sw_clkmgr_sleep_frequency	403.000s	4749.388us	1	1	100.00
chip_sw_clkmgr_reset_frequency				1	1	100.00
	chip_sw_clkmgr_reset_frequency	246.450s	3549.583us	1	1	100.00
chip_sw_clkmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	428.440s	6362.231us	1	1	100.00
chip_sw_clkmgr_alert_handler_clock_enables				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	993.550s	8220.837us	1	1	100.00
chip_sw_csrng_edn_cmd				1	1	100.00
	chip_sw_entropy_src_csrng	2339.580s	24631.522us	1	1	100.00
chip_sw_csrng_fuse_en_sw_app_read				1	1	100.00
	chip_sw_csrng_fuse_en_sw_app_read_test	346.990s	5005.139us	1	1	100.00
chip_sw_csrng_lc_hw_debug_en				1	1	100.00
	chip_sw_csrng_lc_hw_debug_en_test	484.400s	6988.689us	1	1	100.00
chip_sw_csrng_known_answer_tests				1	1	100.00
	chip_sw_csrng_kat_test	186.960s	3225.636us	1	1	100.00
chip_sw_edn_entropy_reqs				3	3	100.00
	chip_sw_csrng_edn_concurrency	5632.060s	31141.502us	1	1	100.00
	chip_sw_entropy_src_ast_rng_req	168.170s	2982.109us	1	1	100.00
	chip_sw_edn_entropy_reqs	853.830s	7644.259us	1	1	100.00
chip_sw_entropy_src_ast_rng_req				1	1	100.00
	chip_sw_entropy_src_ast_rng_req	168.170s	2982.109us	1	1	100.00
chip_sw_entropy_src_csrng				1	1	100.00
	chip_sw_entropy_src_csrng	2339.580s	24631.522us	1	1	100.00
chip_sw_entropy_src_known_answer_tests				1	1	100.00
	chip_sw_entropy_src_kat_test	139.800s	2487.094us	1	1	100.00
chip_sw_flash_init				1	1	100.00
	chip_sw_flash_init	1091.260s	20247.982us	1	1	100.00
chip_sw_flash_host_access				2	2	100.00
	chip_sw_flash_ctrl_access	622.150s	5460.250us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	587.930s	6054.996us	1	1	100.00
chip_sw_flash_ctrl_ops				2	2	100.00
	chip_sw_flash_ctrl_ops	386.370s	3807.942us	1	1	100.00
	chip_sw_flash_ctrl_ops_jitter_en	334.960s	4685.486us	1	1	100.00
chip_sw_flash_rma_unlocked				1	1	100.00
	chip_sw_flash_rma_unlocked	3570.300s	44116.042us	1	1	100.00
chip_sw_flash_scramble				1	1	100.00
	chip_sw_flash_init	1091.260s	20247.982us	1	1	100.00
chip_sw_flash_idle_low_power				1	1	100.00
	chip_sw_flash_ctrl_idle_low_power	194.990s	3437.338us	1	1	100.00
chip_sw_flash_keymgr_seeds				1	1	100.00
	chip_sw_keymgr_key_derivation	1292.500s	9910.774us	1	1	100.00
chip_sw_flash_lc_creator_seed_sw_rw_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	208.490s	3380.178us	0	1	0.00
chip_sw_flash_creator_seed_wipe_on_rma				1	1	100.00
	chip_sw_flash_rma_unlocked	3570.300s	44116.042us	1	1	100.00
chip_sw_flash_lc_owner_seed_sw_rw_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	208.490s	3380.178us	0	1	0.00
chip_sw_flash_lc_iso_part_sw_rd_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	208.490s	3380.178us	0	1	0.00
chip_sw_flash_lc_iso_part_sw_wr_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	208.490s	3380.178us	0	1	0.00
chip_sw_flash_lc_seed_hw_rd_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	208.490s	3380.178us	0	1	0.00
chip_sw_flash_lc_escalate_en				1	1	100.00
	chip_sw_all_escalation_resets	428.440s	6362.231us	1	1	100.00
chip_sw_flash_prim_tl_access				1	1	100.00
	chip_prim_tl_access	442.320s	12758.931us	1	1	100.00
chip_sw_flash_ctrl_clock_freqs				1	1	100.00
	chip_sw_flash_ctrl_clock_freqs	526.650s	5556.456us	1	1	100.00
chip_sw_flash_ctrl_escalation_reset				1	1	100.00
	chip_sw_flash_crash_alert	352.540s	4681.733us	1	1	100.00
chip_sw_flash_ctrl_write_clear				1	1	100.00
	chip_sw_flash_crash_alert	352.540s	4681.733us	1	1	100.00
chip_sw_hmac_enc				2	2	100.00
	chip_sw_hmac_enc	164.510s	2700.038us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	170.800s	3133.476us	1	1	100.00
chip_sw_hmac_idle				1	1	100.00
	chip_sw_hmac_enc_idle	161.430s	2809.858us	1	1	100.00
chip_sw_hmac_all_configurations				1	1	100.00
	chip_sw_hmac_oneshot	946.370s	7643.255us	1	1	100.00
chip_sw_hmac_multistream_mode				1	1	100.00
	chip_sw_hmac_multistream	749.000s	6486.182us	1	1	100.00
chip_sw_i2c_host_tx_rx				3	3	100.00
	chip_sw_i2c_host_tx_rx	401.600s	5494.832us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx1	475.250s	5087.939us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx2	422.310s	5377.441us	1	1	100.00
chip_sw_i2c_device_tx_rx				1	1	100.00
	chip_sw_i2c_device_tx_rx	266.700s	3738.986us	1	1	100.00
chip_sw_keymgr_key_derivation				2	2	100.00
	chip_sw_keymgr_key_derivation	1292.500s	9910.774us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	745.220s	8100.176us	1	1	100.00
chip_sw_keymgr_sideload_kmac				1	1	100.00
	chip_sw_keymgr_sideload_kmac	1511.640s	11433.180us	1	1	100.00
chip_sw_keymgr_sideload_aes				1	1	100.00
	chip_sw_keymgr_sideload_aes	1280.390s	10017.096us	1	1	100.00
chip_sw_keymgr_sideload_otbn				1	1	100.00
	chip_sw_keymgr_sideload_otbn	2159.560s	12218.912us	1	1	100.00
chip_sw_kmac_enc				3	3	100.00
	chip_sw_kmac_mode_cshake	184.260s	3031.937us	1	1	100.00
	chip_sw_kmac_mode_kmac	181.820s	3458.687us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	202.330s	3832.207us	1	1	100.00
chip_sw_kmac_app_keymgr				1	1	100.00
	chip_sw_keymgr_key_derivation	1292.500s	9910.774us	1	1	100.00
chip_sw_kmac_app_lc				1	1	100.00
	chip_sw_lc_ctrl_transition	617.490s	10054.965us	1	1	100.00
chip_sw_kmac_app_rom				1	1	100.00
	chip_sw_kmac_app_rom	132.800s	2279.669us	1	1	100.00
chip_sw_kmac_entropy				1	1	100.00
	chip_sw_kmac_entropy	1279.100s	10433.853us	1	1	100.00
chip_sw_kmac_idle				1	1	100.00
	chip_sw_kmac_idle	169.100s	3399.789us	1	1	100.00
chip_sw_lc_ctrl_alert_handler_escalation				1	1	100.00
	chip_sw_alert_handler_escalation	424.810s	6030.923us	1	1	100.00
chip_sw_lc_ctrl_jtag_access				3	3	100.00
	chip_tap_straps_dev	93.370s	2402.723us	1	1	100.00
	chip_tap_straps_rma	196.130s	4052.433us	1	1	100.00
	chip_tap_straps_prod	90.580s	2828.798us	1	1	100.00
chip_sw_lc_ctrl_otp_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	126.790s	2851.243us	1	1	100.00
chip_sw_lc_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	617.490s	10054.965us	1	1	100.00
chip_sw_lc_ctrl_transitions				1	1	100.00
	chip_sw_lc_ctrl_transition	617.490s	10054.965us	1	1	100.00
chip_sw_lc_ctrl_kmac_req				1	1	100.00
	chip_sw_lc_ctrl_transition	617.490s	10054.965us	1	1	100.00
chip_sw_lc_ctrl_key_div				1	1	100.00
	chip_sw_keymgr_key_derivation_prod	923.260s	8905.545us	1	1	100.00
chip_sw_lc_ctrl_broadcast				19	22	86.36
	chip_sw_flash_ctrl_lc_rw_en	208.490s	3380.178us	0	1	0.00
	chip_sw_flash_rma_unlocked	3570.300s	44116.042us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	238.590s	3573.140us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	446.210s	6120.890us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	663.820s	6965.418us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	405.890s	6196.562us	0	1	0.00
	chip_sw_lc_ctrl_transition	617.490s	10054.965us	1	1	100.00
	chip_sw_keymgr_key_derivation	1292.500s	9910.774us	1	1	100.00
	chip_sw_rom_ctrl_integrity_check	341.830s	10035.256us	1	1	100.00
	chip_sw_sram_ctrl_execution_main	488.290s	7939.991us	1	1	100.00
	chip_prim_tl_access	442.320s	12758.931us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	367.440s	7319.661us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	372.430s	3619.046us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	369.170s	4256.667us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	361.580s	4283.829us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	382.050s	5076.421us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	375.480s	3944.915us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	365.480s	5290.236us	1	1	100.00
	chip_tap_straps_dev	93.370s	2402.723us	1	1	100.00
	chip_tap_straps_rma	196.130s	4052.433us	1	1	100.00
	chip_tap_straps_prod	90.580s	2828.798us	1	1	100.00
	chip_rv_dm_lc_disabled	50.380s	2596.357us	0	1	0.00
chip_lc_scrap				4	4	100.00
	chip_sw_lc_ctrl_rma_to_scrap	158.830s	3392.930us	1	1	100.00
	chip_sw_lc_ctrl_raw_to_scrap	98.270s	3389.038us	1	1	100.00
	chip_sw_lc_ctrl_test_locked0_to_scrap	77.110s	3086.230us	1	1	100.00
	chip_sw_lc_ctrl_rand_to_scrap	112.740s	3132.583us	1	1	100.00
chip_lc_test_locked				1	2	50.00
	chip_sw_lc_walkthrough_testunlocks	1983.340s	37246.911us	1	1	100.00
	chip_rv_dm_lc_disabled	50.380s	2596.357us	0	1	0.00
chip_sw_lc_walkthrough				2	5	40.00
	chip_sw_lc_walkthrough_dev	621.890s	10574.622us	0	1	0.00
	chip_sw_lc_walkthrough_prod	610.200s	9220.363us	0	1	0.00
	chip_sw_lc_walkthrough_prodend	603.300s	9735.328us	1	1	100.00
	chip_sw_lc_walkthrough_rma	353.320s	5841.396us	0	1	0.00
	chip_sw_lc_walkthrough_testunlocks	1983.340s	37246.911us	1	1	100.00
chip_sw_lc_ctrl_volatile_raw_unlock				2	3	66.67
	chip_sw_lc_ctrl_volatile_raw_unlock	61.570s	2707.094us	1	1	100.00
	chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	60.890s	1949.913us	1	1	100.00
	rom_volatile_raw_unlock	99.434s	0.000us	0	1	0.00
chip_sw_otbn_op				2	2	100.00
	chip_sw_otbn_ecdsa_op_irq	3456.330s	17098.833us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3565.720s	19561.179us	1	1	100.00
chip_sw_otbn_rnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	552.810s	5901.223us	1	1	100.00
chip_sw_otbn_urnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	552.810s	5901.223us	1	1	100.00
chip_sw_otbn_idle				1	1	100.00
	chip_sw_otbn_randomness	552.810s	5901.223us	1	1	100.00
chip_sw_otbn_mem_scramble				1	1	100.00
	chip_sw_otbn_mem_scramble	303.190s	4539.902us	1	1	100.00
chip_otp_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	617.490s	10054.965us	1	1	100.00
chip_sw_otp_ctrl_keys				5	5	100.00
	chip_sw_flash_init	1091.260s	20247.982us	1	1	100.00
	chip_sw_otbn_mem_scramble	303.190s	4539.902us	1	1	100.00
	chip_sw_keymgr_key_derivation	1292.500s	9910.774us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	401.170s	5094.012us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	156.210s	3030.604us	1	1	100.00
chip_sw_otp_ctrl_entropy				5	5	100.00
	chip_sw_flash_init	1091.260s	20247.982us	1	1	100.00
	chip_sw_otbn_mem_scramble	303.190s	4539.902us	1	1	100.00
	chip_sw_keymgr_key_derivation	1292.500s	9910.774us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	401.170s	5094.012us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	156.210s	3030.604us	1	1	100.00
chip_sw_otp_ctrl_program				1	1	100.00
	chip_sw_lc_ctrl_transition	617.490s	10054.965us	1	1	100.00
chip_sw_otp_ctrl_program_error				1	1	100.00
	chip_sw_lc_ctrl_program_error	292.940s	4209.477us	1	1	100.00
chip_sw_otp_ctrl_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	126.790s	2851.243us	1	1	100.00
chip_sw_otp_ctrl_lc_signals				5	6	83.33
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	238.590s	3573.140us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	446.210s	6120.890us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	663.820s	6965.418us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	405.890s	6196.562us	0	1	0.00
	chip_sw_lc_ctrl_transition	617.490s	10054.965us	1	1	100.00
	chip_prim_tl_access	442.320s	12758.931us	1	1	100.00
chip_sw_otp_prim_tl_access				1	1	100.00
	chip_prim_tl_access	442.320s	12758.931us	1	1	100.00
chip_sw_otp_ctrl_dai_lock				1	1	100.00
	chip_sw_otp_ctrl_dai_lock	853.410s	7303.364us	1	1	100.00
chip_sw_pwrmgr_external_full_reset				0	1	0.00
	chip_sw_pwrmgr_full_aon_reset	64.630s	2886.179us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_wake_ups	912.280s	24688.866us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_all_wake_ups	295.120s	7545.728us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_por_reset				0	1	0.00
	chip_sw_pwrmgr_deep_sleep_por_reset	366.840s	7503.547us	0	1	0.00
chip_sw_pwrmgr_normal_sleep_por_reset				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_por_reset	314.290s	5979.018us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_all_wake_ups	1258.910s	25492.402us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs				2	2	100.00
	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	1082.130s	15343.911us	1	1	100.00
	chip_sw_aon_timer_wdog_bite_reset	471.950s	7172.708us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	714.260s	10684.288us	1	1	100.00
chip_sw_pwrmgr_wdog_reset				1	1	100.00
	chip_sw_pwrmgr_wdog_reset	412.810s	5706.711us	1	1	100.00
chip_sw_pwrmgr_aon_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_full_aon_reset	64.630s	2886.179us	0	1	0.00
chip_sw_pwrmgr_main_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_main_power_glitch_reset	219.560s	4160.985us	1	1	100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	2388.450s	28318.260us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	311.770s	7233.897us	1	1	100.00
chip_sw_pwrmgr_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_sleep_power_glitch_reset	185.860s	3254.903us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs				0	1	0.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	212.310s	5268.145us	0	1	0.00
chip_sw_pwrmgr_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	656.750s	6951.347us	1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	834.550s	9891.699us	1	1	100.00
chip_sw_pwrmgr_b2b_sleep_reset_req				1	1	100.00
	chip_sw_pwrmgr_b2b_sleep_reset_req	1710.340s	27465.534us	1	1	100.00
chip_sw_pwrmgr_sleep_disabled				1	1	100.00
	chip_sw_pwrmgr_sleep_disabled	150.350s	3336.560us	1	1	100.00
chip_sw_pwrmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	428.440s	6362.231us	1	1	100.00
chip_sw_rom_access				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	341.830s	10035.256us	1	1	100.00
chip_sw_rom_ctrl_integrity_check				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	341.830s	10035.256us	1	1	100.00
chip_sw_rstmgr_non_sys_reset_info				3	4	75.00
	chip_sw_pwrmgr_all_reset_reqs	834.550s	9891.699us	1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	212.310s	5268.145us	0	1	0.00
	chip_sw_pwrmgr_wdog_reset	412.810s	5706.711us	1	1	100.00
	chip_sw_pwrmgr_smoketest	268.530s	5215.823us	1	1	100.00
chip_sw_rstmgr_sys_reset_info				1	1	100.00
	chip_rv_dm_ndm_reset_req	338.260s	4992.631us	1	1	100.00
chip_sw_rstmgr_cpu_info				1	1	100.00
	chip_sw_rstmgr_cpu_info	450.500s	6438.581us	1	1	100.00
chip_sw_rstmgr_sw_req_reset				1	1	100.00
	chip_sw_rstmgr_sw_req	308.280s	4646.953us	1	1	100.00
chip_sw_rstmgr_alert_info				1	1	100.00
	chip_sw_rstmgr_alert_info	1074.440s	11932.821us	1	1	100.00
chip_sw_rstmgr_sw_rst				1	1	100.00
	chip_sw_rstmgr_sw_rst	180.650s	3489.088us	1	1	100.00
chip_sw_rstmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	428.440s	6362.231us	1	1	100.00
chip_sw_rstmgr_alert_handler_reset_enables				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	868.710s	6853.544us	1	1	100.00
chip_sw_nmi_irq				1	1	100.00
	chip_sw_rv_core_ibex_nmi_irq	456.230s	5090.517us	1	1	100.00
chip_sw_rv_core_ibex_rnd				1	1	100.00
	chip_sw_rv_core_ibex_rnd	508.260s	5229.521us	1	1	100.00
chip_sw_rv_core_ibex_address_translation				1	1	100.00
	chip_sw_rv_core_ibex_address_translation	187.040s	3833.811us	1	1	100.00
chip_sw_rv_core_ibex_icache_scrambled_access				1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	156.210s	3030.604us	1	1	100.00
chip_sw_rv_core_ibex_fault_dump				1	1	100.00
	chip_sw_rstmgr_cpu_info	450.500s	6438.581us	1	1	100.00
chip_sw_rv_core_ibex_double_fault				1	1	100.00
	chip_sw_rstmgr_cpu_info	450.500s	6438.581us	1	1	100.00
chip_jtag_csr_rw				1	1	100.00
	chip_jtag_csr_rw	570.660s	9262.335us	1	1	100.00
chip_jtag_mem_access				1	1	100.00
	chip_jtag_mem_access	915.980s	13530.226us	1	1	100.00
chip_rv_dm_ndm_reset_req				1	1	100.00
	chip_rv_dm_ndm_reset_req	338.260s	4992.631us	1	1	100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted				0	1	0.00
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	204.390s	3242.790us	0	1	0.00
chip_rv_dm_access_after_wakeup				1	1	100.00
	chip_sw_rv_dm_access_after_wakeup	356.950s	6679.296us	1	1	100.00
chip_sw_rv_dm_jtag_tap_sel				1	1	100.00
	chip_tap_straps_rma	196.130s	4052.433us	1	1	100.00
chip_rv_dm_lc_disabled				0	1	0.00
	chip_rv_dm_lc_disabled	50.380s	2596.357us	0	1	0.00
chip_sw_plic_all_irqs				3	3	100.00
	chip_plic_all_irqs_0	566.460s	5550.430us	1	1	100.00
	chip_plic_all_irqs_10	238.160s	3238.412us	1	1	100.00
	chip_plic_all_irqs_20	359.690s	4606.859us	1	1	100.00
chip_sw_plic_sw_irq				1	1	100.00
	chip_sw_plic_sw_irq	183.530s	3302.616us	1	1	100.00
chip_sw_timer				1	1	100.00
	chip_sw_rv_timer_irq	179.180s	3534.920us	1	1	100.00
chip_sw_spi_device_flash_mode				1	1	100.00
	rom_e2e_smoke	3213.050s	17055.974us	1	1	100.00
chip_sw_spi_device_pass_through				1	1	100.00
	chip_sw_spi_device_pass_through	410.460s	7336.123us	1	1	100.00
chip_sw_spi_device_pass_through_collision				0	1	0.00
	chip_sw_spi_device_pass_through_collision	196.800s	2958.914us	0	1	0.00
chip_sw_spi_device_tpm				1	1	100.00
	chip_sw_spi_device_tpm	194.640s	3737.414us	1	1	100.00
chip_sw_spi_host_tx_rx				1	1	100.00
	chip_sw_spi_host_tx_rx	193.300s	3244.912us	1	1	100.00
chip_sw_sram_scrambled_access				2	2	100.00
	chip_sw_sram_ctrl_scrambled_access	401.170s	5094.012us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	312.130s	4095.897us	1	1	100.00
chip_sw_sleep_sram_ret_contents				2	2	100.00
	chip_sw_sleep_sram_ret_contents_no_scramble	431.990s	7941.844us	1	1	100.00
	chip_sw_sleep_sram_ret_contents_scramble	438.940s	7647.905us	1	1	100.00
chip_sw_sram_execution				1	1	100.00
	chip_sw_sram_ctrl_execution_main	488.290s	7939.991us	1	1	100.00
chip_sw_sram_lc_escalation				2	2	100.00
	chip_sw_all_escalation_resets	428.440s	6362.231us	1	1	100.00
	chip_sw_data_integrity_escalation	461.680s	5370.845us	1	1	100.00
chip_sw_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	656.750s	6951.347us	1	1	100.00
	chip_sw_sysrst_ctrl_reset	1167.890s	24086.468us	1	1	100.00
chip_sw_sysrst_ctrl_inputs				1	1	100.00
	chip_sw_sysrst_ctrl_inputs	134.390s	2274.745us	1	1	100.00
chip_sw_sysrst_ctrl_outputs				1	1	100.00
	chip_sw_sysrst_ctrl_outputs	240.260s	3836.942us	1	1	100.00
chip_sw_sysrst_ctrl_in_irq				1	1	100.00
	chip_sw_sysrst_ctrl_in_irq	315.140s	4711.049us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_wakeup				1	1	100.00
	chip_sw_sysrst_ctrl_reset	1167.890s	24086.468us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_reset				1	1	100.00
	chip_sw_sysrst_ctrl_reset	1167.890s	24086.468us	1	1	100.00
chip_sw_sysrst_ctrl_ec_rst_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2337.300s	21057.196us	1	1	100.00
chip_sw_sysrst_ctrl_flash_wp_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2337.300s	21057.196us	1	1	100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup				1	2	50.00
	chip_sw_sysrst_ctrl_ulp_z3_wakeup	343.360s	6464.823us	1	1	100.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3272.030s	34386.077us	0	1	0.00
chip_sw_usbdev_vbus				1	1	100.00
	chip_sw_usbdev_vbus	177.190s	3791.422us	1	1	100.00
chip_sw_usbdev_pullup				1	1	100.00
	chip_sw_usbdev_pullup	149.030s	3023.521us	1	1	100.00
chip_sw_usbdev_aon_pullup				1	1	100.00
	chip_sw_usbdev_aon_pullup	278.630s	3789.667us	1	1	100.00
chip_sw_usbdev_setup_rx				1	1	100.00
	chip_sw_usbdev_setuprx	333.460s	4092.715us	1	1	100.00
chip_sw_usbdev_config_host				1	1	100.00
	chip_sw_usbdev_config_host	951.820s	7755.078us	1	1	100.00
chip_sw_usbdev_pincfg				1	1	100.00
	chip_sw_usbdev_pincfg	5514.120s	32570.856us	1	1	100.00
chip_sw_usbdev_tx_rx				1	1	100.00
	chip_sw_usbdev_dpi	1811.830s	11299.000us	1	1	100.00
chip_sw_usbdev_toggle_restore				1	1	100.00
	chip_sw_usbdev_toggle_restore	159.770s	3189.107us	1	1	100.00

V2S

1/2 passed

50.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_aes_masking_off				1	1	100.00
	chip_sw_aes_masking_off	220.000s	3180.431us	1	1	100.00
chip_sw_rv_core_ibex_lockstep_glitch				0	1	0.00
	chip_sw_rv_core_ibex_lockstep_glitch	99.130s	2131.426us	0	1	0.00

17/26 passed

65.38 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_coremark				1	1	100.00
	chip_sw_coremark	10199.760s	72120.063us	1	1	100.00
chip_sw_power_max_load				1	1	100.00
	chip_sw_power_virus	1130.510s	6547.075us	1	1	100.00
rom_e2e_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	184.390s	4221.107us	0	1	0.00
	rom_e2e_jtag_debug_dev	146.650s	4399.932us	0	1	0.00
	rom_e2e_jtag_debug_rma	163.600s	3172.411us	0	1	0.00
rom_e2e_jtag_inject				0	3	0.00
	rom_e2e_jtag_inject_test_unlocked0	77.090s	2158.510us	0	1	0.00
	rom_e2e_jtag_inject_dev	61.730s	2966.011us	0	1	0.00
	rom_e2e_jtag_inject_rma	78.180s	2758.900us	0	1	0.00
rom_e2e_self_hash				0	1	0.00
	rom_e2e_self_hash	48.993s	0.000us	0	1	0.00
chip_sw_clkmgr_jitter_cycle_measurements				0	1	0.00
	chip_sw_clkmgr_jitter_frequency	310.780s	3989.128us	0	1	0.00
chip_sw_edn_boot_mode				1	1	100.00
	chip_sw_edn_boot_mode	288.190s	3211.725us	1	1	100.00
chip_sw_edn_auto_mode				1	1	100.00
	chip_sw_edn_auto_mode	429.440s	3513.943us	1	1	100.00
chip_sw_edn_sw_mode				1	1	100.00
	chip_sw_edn_sw_mode	1511.920s	10468.086us	1	1	100.00
chip_sw_edn_kat				1	1	100.00
	chip_sw_edn_kat	223.770s	2428.639us	1	1	100.00
chip_sw_flash_memory_protection				1	1	100.00
	chip_sw_flash_ctrl_mem_protection	587.560s	5168.372us	1	1	100.00
chip_sw_otp_ctrl_vendor_test_csr_access				1	1	100.00
	chip_sw_otp_ctrl_vendor_test_csr_access	62.900s	2165.844us	1	1	100.00
chip_sw_otp_ctrl_escalation				0	1	0.00
	chip_sw_otp_ctrl_escalation	185.550s	2988.800us	0	1	0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up				1	1	100.00
	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	335.570s	6871.695us	1	1	100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active				1	1	100.00
	chip_sw_pwrmgr_usb_clk_disabled_when_active	315.000s	5481.767us	1	1	100.00
chip_sw_all_resets				1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	834.550s	9891.699us	1	1	100.00
chip_rv_dm_perform_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	184.390s	4221.107us	0	1	0.00
	rom_e2e_jtag_debug_dev	146.650s	4399.932us	0	1	0.00
	rom_e2e_jtag_debug_rma	163.600s	3172.411us	0	1	0.00
chip_sw_rv_dm_access_after_hw_reset				1	1	100.00
	chip_sw_rv_dm_access_after_escalation_reset	426.750s	5109.368us	1	1	100.00
chip_sw_plic_alerts				1	1	100.00
	chip_sw_all_escalation_resets	428.440s	6362.231us	1	1	100.00
tick_configuration				1	1	100.00
	chip_sw_rv_timer_systick_test	5451.560s	38218.945us	1	1	100.00
counter_wrap				1	1	100.00
	chip_sw_rv_timer_systick_test	5451.560s	38218.945us	1	1	100.00
chip_sw_spi_device_output_when_disabled_or_sleeping				1	1	100.00
	chip_sw_spi_device_pinmux_sleep_retention	177.680s	3798.149us	1	1	100.00
chip_sw_uart_watermarks				1	1	100.00
	chip_sw_uart_tx_rx	401.780s	4603.665us	1	1	100.00
chip_sw_usbdev_stream				1	1	100.00
	chip_sw_usbdev_stream	3025.480s	19116.537us	1	1	100.00

unmapped

8/10 passed

80.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				8	10	80.00
	chip_sival_flash_info_access	212.260s	3321.492us	1	1	100.00
	chip_sw_rstmgr_rst_cnsty_escalation	334.880s	5261.307us	1	1	100.00
	chip_sw_otp_ctrl_rot_auth_config	4.520s	0.000us	0	1	0.00
	chip_sw_otp_ctrl_ecc_error_vendor_test	161.670s	3295.993us	1	1	100.00
	chip_sw_otp_ctrl_descrambling	189.910s	3375.021us	1	1	100.00
	chip_sw_pwrmgr_lowpower_cancel	281.970s	3697.078us	1	1	100.00
	chip_sw_pwrmgr_sleep_wake_5_bug	7.689s	0.000us	0	1	0.00
	chip_sw_flash_ctrl_write_clear	210.410s	3751.222us	1	1	100.00
	ate_bootstrap_flash_erase	6673.090s	45310.405us	1	1	100.00
	ate_bootstrap_disjoint	9287.400s	84381.974us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [] vs xz [z]) for MIO[*]
	chip_sw_sleep_pin_mio_dio_val	79852752166468659934462665617334098371187330186781280197807157307996712403138	451	UVM_INFO @ 3158.034500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
	chip_sw_spi_device_pass_through_collision	85178790265036683211334554399102758980121107155009158132567897413010974845052	320	UVM_INFO @ 2958.914414 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
	chip_sw_flash_ctrl_lc_rw_en	88754577601980285349665377067468161922261917690558695955135277096381896712638	309	UVM_INFO @ 3380.178036 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *
	chip_sw_otp_ctrl_lc_signals_rma	83245393921481650223177866173670153383825910927564592128669169008954330508225	342	UVM_INFO @ 6196.561946 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
	chip_sw_otp_ctrl_escalation	58510406924208495294041408065520425368179422320361810200426412633565264627235	316	UVM_ERROR @ 2988.799732 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A UVM_INFO @ 2988.799732 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode
	chip_sw_otp_ctrl_rot_auth_config	30485692999244108766290990998368750764640127423257385542113874693896421981669	282	UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
	chip_sw_lc_walkthrough_dev	46881630300297531947752566345082614587052707168327440225764999809002262156935	369	UVM_INFO @ 10574.622368 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_prod	15406169325940457335819919519301309937663971293265693236613431920160602427198	369	UVM_INFO @ 9220.362974 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_rma	15562881140967613977395736897244245030510945294566487928486867110221338772587	341	UVM_INFO @ 5841.395620 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))'
	chip_sw_pwrmgr_full_aon_reset	95678379168558045480410721531878495986657033666706054752161192305850331758224	303	UVM_ERROR @ 2886.179336 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A UVM_INFO @ 2886.179336 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	108392865893507996376552307973971035038852917420487281895239212589799222798150	315	UVM_ERROR @ 5268.145000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 5268.145000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_deep_sleep_por_reset	57945491347613948611468860901919789444726297131152397177093781345577218861714	325	UVM_ERROR @ 7503.547000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 7503.547000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))'
	chip_sw_pwrmgr_sleep_power_glitch_reset	106502359014348743261457571315526966257787729768636817111868585364284167733745	313	UVM_ERROR @ 3254.902509 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A UVM_INFO @ 3254.902509 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	68423753655153450176113281415468944925292011007691694331412202588721596368933	332	UVM_INFO @ 34386.076689 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:352)] CHECK-fail: Expect alert *!
	chip_sw_alert_test	60765302269619551492434997134048660534803578331993164890377266397073328214260	307	UVM_INFO @ 2835.144587 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
	chip_sw_alert_handler_lpg_sleep_mode_alerts	51521718770311851194410237005070869771886406465361783523379376420018015472044	308	UVM_INFO @ 2482.669240 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job killed!
	chip_sw_alert_handler_lpg_sleep_mode_pings	4550445062432191836446627125738425923403562754522537491854857187042536416314	None
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted , but saw ).
	chip_tl_errors	23306282727954456596801541446534860745145273865633974354730381814758420445776	217	TL item was: req: (cip_tl_seq_item@33731) { a_addr: 'h1044c a_data: 'h547bb153 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3f a_opcode: 'h4 a_user: 'h1a503 d_param: 'h0 d_source: 'h3f d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 } Reasons for predicted error: '{"Fetch from CSR"} . UVM_INFO @ 1909.755260 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
	chip_sw_clkmgr_jitter_frequency	23767605706180904045857190211952196011902073685369257939480801689168420038918	343	UVM_INFO @ 3989.127909 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']
	chip_sw_pwrmgr_sleep_wake_5_bug	26248016629006193168227980033687164995452771402785419046648414754205053629201	None	---- STDERR ---- Another command (pid=2074117) is running. Waiting for it to complete on the server (server_pid=247531)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	105809200174018271710157996591192568534070689937976688839588613905414601490915	None	---- STDERR ---- Another command (pid=352472) is running. Waiting for it to complete on the server (server_pid=247531)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_dev	23982374641623465035407491557674156203584960312158039581658397698200353972647	None	Another command (pid=445861) is running. Waiting for it to complete on the server (server_pid=247531)... Another command (pid=547641) is running. Waiting for it to complete on the server (server_pid=247531)... Another command (pid=570255) is running. Waiting for it to complete on the server (server_pid=247531)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_prod	2019402713683475045172453398840763551524386152323515404371175654936448556287	None	Another command (pid=594799) is running. Waiting for it to complete on the server (server_pid=247531)... Another command (pid=559816) is running. Waiting for it to complete on the server (server_pid=247531)... Another command (pid=595718) is running. Waiting for it to complete on the server (server_pid=247531)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	47172557486284935986049194881301794471020677249359899261170834169248758471029	None	Another command (pid=573064) is running. Waiting for it to complete on the server (server_pid=247531)... Another command (pid=535652) is running. Waiting for it to complete on the server (server_pid=247531)... Another command (pid=583974) is running. Waiting for it to complete on the server (server_pid=247531)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_rma	103965490554671328086809215498823423825907184115664195514059217946381080317706	None	Another command (pid=547641) is running. Waiting for it to complete on the server (server_pid=247531)... Another command (pid=570255) is running. Waiting for it to complete on the server (server_pid=247531)... Another command (pid=573064) is running. Waiting for it to complete on the server (server_pid=247531)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	72467528930020251081522950437735104135184475858221818561815650592959093959096	None	Another command (pid=441417) is running. Waiting for it to complete on the server (server_pid=247531)... Another command (pid=441784) is running. Waiting for it to complete on the server (server_pid=247531)... Another command (pid=407427) is running. Waiting for it to complete on the server (server_pid=247531)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	21216674738641670103031134552840136893554268362066062718162433054052953573073	None	Another command (pid=440014) is running. Waiting for it to complete on the server (server_pid=247531)... Another command (pid=532695) is running. Waiting for it to complete on the server (server_pid=247531)... Another command (pid=462314) is running. Waiting for it to complete on the server (server_pid=247531)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	85026281023084929291305612004452327741539352334476976962567738397518431577991	None	Another command (pid=407427) is running. Waiting for it to complete on the server (server_pid=247531)... Another command (pid=368797) is running. Waiting for it to complete on the server (server_pid=247531)... Another command (pid=458813) is running. Waiting for it to complete on the server (server_pid=247531)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	59067367704504169550165813720202614559777046084694224536390020615667593442941	None	Another command (pid=442049) is running. Waiting for it to complete on the server (server_pid=247531)... Another command (pid=397009) is running. Waiting for it to complete on the server (server_pid=247531)... Another command (pid=536024) is running. Waiting for it to complete on the server (server_pid=247531)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	28055574580395619136271938075457126662203784228233182297945784975720021498490	None	---- STDERR ---- Another command (pid=441417) is running. Waiting for it to complete on the server (server_pid=247531)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	53424310077568694220954451353942221806315188970504482018572959825608027522871	None	Another command (pid=441417) is running. Waiting for it to complete on the server (server_pid=247531)... Another command (pid=436380) is running. Waiting for it to complete on the server (server_pid=247531)... Another command (pid=407427) is running. Waiting for it to complete on the server (server_pid=247531)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	33116362973167421921478326522046821826741474001332007658990639462543194886550	None	Another command (pid=580380) is running. Waiting for it to complete on the server (server_pid=247531)... Another command (pid=615664) is running. Waiting for it to complete on the server (server_pid=247531)... Another command (pid=612742) is running. Waiting for it to complete on the server (server_pid=247531)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	111637200163196915205215254902032967016119508710023459953061653947966048981366	None	Another command (pid=581251) is running. Waiting for it to complete on the server (server_pid=247531)... Another command (pid=385422) is running. Waiting for it to complete on the server (server_pid=247531)... Another command (pid=594799) is running. Waiting for it to complete on the server (server_pid=247531)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	148504568984125934162154668125032781253589238347471192535441697739694445935	None	---- STDERR ---- Another command (pid=462314) is running. Waiting for it to complete on the server (server_pid=247531)... Another command (pid=469769) is running. Waiting for it to complete on the server (server_pid=247531)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	28966098204981898549725447139109584950310435268473918168087408615539418427995	None	Another command (pid=445861) is running. Waiting for it to complete on the server (server_pid=247531)... Another command (pid=547641) is running. Waiting for it to complete on the server (server_pid=247531)... Another command (pid=570255) is running. Waiting for it to complete on the server (server_pid=247531)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_test_unlocked0	45025879440369954758970567550077405634338584790877983312511416055681031734766	None	Another command (pid=557272) is running. Waiting for it to complete on the server (server_pid=247531)... Another command (pid=594799) is running. Waiting for it to complete on the server (server_pid=247531)... Another command (pid=559816) is running. Waiting for it to complete on the server (server_pid=247531)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_dev	66455030867012254299050548609987232125178185156754081176864016533625291342590	None	Another command (pid=364879) is running. Waiting for it to complete on the server (server_pid=247531)... Another command (pid=367509) is running. Waiting for it to complete on the server (server_pid=247531)... Another command (pid=424641) is running. Waiting for it to complete on the server (server_pid=247531)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_prod	60078748319228706987748368090503887493193307613067882196665574172054086018940	None	Another command (pid=535065) is running. Waiting for it to complete on the server (server_pid=247531)... Another command (pid=536024) is running. Waiting for it to complete on the server (server_pid=247531)... Another command (pid=422233) is running. Waiting for it to complete on the server (server_pid=247531)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_prod_end	14412629548156050979968936792492333181831549441230889255295211931280519655937	None	Another command (pid=418953) is running. Waiting for it to complete on the server (server_pid=247531)... Another command (pid=420883) is running. Waiting for it to complete on the server (server_pid=247531)... Another command (pid=441417) is running. Waiting for it to complete on the server (server_pid=247531)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_rma	60970323358199802942827577693432375392652194887064578346757238464877218823920	None	---- STDERR ---- Another command (pid=420883) is running. Waiting for it to complete on the server (server_pid=247531)... Another command (pid=441417) is running. Waiting for it to complete on the server (server_pid=247531)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_volatile_raw_unlock	90953731776348964717828089170323829972855501327771969432199148794715343153427	None	Another command (pid=418953) is running. Waiting for it to complete on the server (server_pid=247531)... Another command (pid=420883) is running. Waiting for it to complete on the server (server_pid=247531)... Another command (pid=441417) is running. Waiting for it to complete on the server (server_pid=247531)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_raw_unlock	92026456191682773632778561764344814384573388514667771296951603027573110771090	None	Another command (pid=399121) is running. Waiting for it to complete on the server (server_pid=247531)... Another command (pid=388603) is running. Waiting for it to complete on the server (server_pid=247531)... Another command (pid=364879) is running. Waiting for it to complete on the server (server_pid=247531)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_self_hash	17940619861464742583382392440549462310189912303938285974420534994011813877273	None	---- STDERR ---- Another command (pid=352472) is running. Waiting for it to complete on the server (server_pid=247531)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	55859400938449994017120623440481323998068896050459050611913503288682090729534	327	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_dev	13007376533001722690027791571359447848045578184763631973515949899597855933492	319	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_rma	60494404398182483270733785519952480725436701322952240777042138548046592649180	319	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_test_unlocked0	47816605789768684482092274659617191454364177587915935344275862310594794859543	305	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_dev	45791644562580634098943199360246348266720251924491562559099738518540421817395	303	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_rma	112665803972803652669109975661832751078046283424107664513611337081237705894370	303	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
UVM_ERROR @ * us: (cip_base_vseq.sv:649) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [] vs []) addr read out mismatch
	chip_rv_dm_lc_disabled	61684344420765633855852556372416298039218493708156268095472868811086642651039	215	UVM_INFO @ 2596.356746 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:738) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [] vs [*]) Major alert did not match expectation.
	chip_sw_rv_core_ibex_lockstep_glitch	104456494600405594753130625023773717389489694639695505235761666911883332261252	324	UVM_INFO @ 2131.426462 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
	chip_sw_power_idle_load	50592814404148955727740499210372864316494354696861156894050065873565658105598	312	UVM_INFO @ 3293.733000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
	chip_sw_power_sleep_load	47412185946546483243147861641912802779392370992894656688422011199881035205731	318	UVM_INFO @ 2922.502000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *
	chip_sw_ast_clk_rst_inputs	96980222347964935820849185984998549159664729578184375683113966988269160619230	327	UVM_INFO @ 9006.910781 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_.signed..scr.vmem could not be opened for r mode
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	3891509516273008837386600605563309441118945791195543510855721118590354649325	362	UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	18971027484533962411642476231342306801279578014776745135793705873522495513491	325	UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_.signed..scr.vmem could not be opened for r mode
	rom_e2e_sigverify_always_a_bad_b_bad_dev	113222591971758361658803475404294217159447355836287902025912651113780446928935	367	UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	55360420479122487072939577007454950702839425818362569440123965346391287539162	328	UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_.signed..scr.vmem could not be opened for r mode
	rom_e2e_sigverify_always_a_bad_b_bad_prod	84437925510963004900967735342647489377526263511179094720434000842283705365693	368	UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	13255600552997351550061628001310427069471180362777348459522768873462814009561	365	UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_bad_rma	53934190059337135038290134195965006480659905687007480436131451613689107072385	368	UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	33988670989681349161098188954168579912709047780161026342606923598516998678383	326	UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	73030367663935401854270349945583949689928189759470536746107118964823766765496	328	UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	39018065716827835484686076539301038828961163624187984873559436384198415114417	327	UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_.signed..scr.vmem could not be opened for r mode
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	253924003547901101289325555168858552010013550097937638439887115411521504519	325	UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_.signed..scr.vmem could not be opened for r mode
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	59914102076312498438675082651811864661170389484646202780667322214695025983946	327	UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_.signed..scr.vmem could not be opened for r mode
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	39441297168418099325137888523517702644995850301096870249447195472054454029140	326	UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	34469217415687733443855735024936897339906076079441152667177694153243363410406	326	UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	31496038450135104239405799176662796993867993613967321149382053155103734260398	326	UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_rv_debugger.sv:784) [debugger] Index * appears to be out of bounds
	rom_e2e_jtag_debug_test_unlocked0	2625753940984060352417225084971316937039255622782389446533281747816060063268	318	UVM_INFO @ 4221.106542 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *
	rom_e2e_keymgr_init_rom_ext_meas	107863172424968835172998751562504890286634241896457020413179818441462966712123	319	UVM_INFO @ 17131.878048 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *
	rom_e2e_keymgr_init_rom_ext_no_meas	35797802361696987605453705186594767202229301941611780090633805576095455289814	319	UVM_INFO @ 16592.982344 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '$stable(key_data_i)'
	rom_keymgr_functest	25848385784941348211626037181661865897757993744566163557457737741785344310088	327	UVM_ERROR @ 4930.483328 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M UVM_INFO @ 4930.483328 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---