Simulation Results: clkmgr

 
30/04/2026 15:30:31 DVSim: v1.33.0 sha: c776b8b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.55 %
  • code
  • 97.70 %
  • assert
  • 93.08 %
  • func
  • 83.88 %
  • line
  • 98.99 %
  • branch
  • 98.99 %
  • cond
  • 90.50 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
91.67%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.750s 28.085us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.690s 20.084us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.800s 23.074us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 3.330s 720.024us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.430s 29.969us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.360s 145.810us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.800s 23.074us 1 1 100.00
clkmgr_csr_aliasing 1.430s 29.969us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.990s 159.211us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.920s 60.301us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.780s 18.069us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.730s 47.494us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.750s 28.085us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 8.690s 1759.828us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 6.300s 1704.869us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 8.690s 1759.828us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 12.670s 2745.230us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.820s 52.132us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.730s 213.897us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.730s 213.897us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.690s 20.084us 1 1 100.00
clkmgr_csr_rw 0.800s 23.074us 1 1 100.00
clkmgr_csr_aliasing 1.430s 29.969us 1 1 100.00
clkmgr_same_csr_outstanding 0.950s 54.362us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.690s 20.084us 1 1 100.00
clkmgr_csr_rw 0.800s 23.074us 1 1 100.00
clkmgr_csr_aliasing 1.430s 29.969us 1 1 100.00
clkmgr_same_csr_outstanding 0.950s 54.362us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
clkmgr_sec_cm 3.150s 699.731us 1 1 100.00
clkmgr_tl_intg_err 1.500s 151.063us 1 1 100.00
shadow_reg_update_error 0 1 0.00
clkmgr_shadow_reg_errors 1.140s 133.334us 0 1 0.00
shadow_reg_read_clear_staged_value 0 1 0.00
clkmgr_shadow_reg_errors 1.140s 133.334us 0 1 0.00
shadow_reg_storage_error 0 1 0.00
clkmgr_shadow_reg_errors 1.140s 133.334us 0 1 0.00
shadowed_reset_glitch 0 1 0.00
clkmgr_shadow_reg_errors 1.140s 133.334us 0 1 0.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 1.890s 204.659us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 1.500s 151.063us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 8.690s 1759.828us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 6.300s 1704.869us 1 1 100.00
sec_cm_meas_config_shadow 0 1 0.00
clkmgr_shadow_reg_errors 1.140s 133.334us 0 1 0.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.890s 21.935us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.790s 50.816us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.740s 21.003us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.750s 17.753us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.750s 34.735us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.800s 23.074us 1 1 100.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 3.150s 699.731us 1 1 100.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.800s 23.074us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.800s 23.074us 1 1 100.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 3.150s 699.731us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 0.900s 75.323us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 35.380s 4028.820us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (alert_receiver_driver.sv:218) [driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
clkmgr_shadow_reg_errors 5400529199354760365368156545996022111868600450167388946144201701854426452380 75
UVM_INFO @ 133334472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---