Simulation Results: csrng

 
30/04/2026 15:30:31 DVSim: v1.33.0 sha: c776b8b json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.14 %
  • code
  • 92.33 %
  • assert
  • 93.23 %
  • func
  • 75.85 %
  • block
  • 97.05 %
  • line
  • 97.80 %
  • branch
  • 92.59 %
  • toggle
  • 93.24 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
91.67%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 3.000s 82.427us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 42.948us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 21.577us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 9.000s 405.900us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 3.000s 90.490us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 1.000s 32.099us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 21.577us 1 1 100.00
csrng_csr_aliasing 3.000s 90.490us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 5.000s 336.749us 1 1 100.00
alerts 1 1 100.00
csrng_alert 8.000s 377.735us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 81.807us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 3.000s 127.731us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 3.000s 127.731us 0 1 0.00
stress_all 1 1 100.00
csrng_stress_all 92.000s 4983.484us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 1.000s 14.440us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 3.000s 98.519us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 4.000s 123.312us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 4.000s 123.312us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 42.948us 1 1 100.00
csrng_csr_rw 2.000s 21.577us 1 1 100.00
csrng_csr_aliasing 3.000s 90.490us 1 1 100.00
csrng_same_csr_outstanding 3.000s 157.520us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 42.948us 1 1 100.00
csrng_csr_rw 2.000s 21.577us 1 1 100.00
csrng_csr_aliasing 3.000s 90.490us 1 1 100.00
csrng_same_csr_outstanding 3.000s 157.520us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 2.000s 68.140us 1 1 100.00
csrng_tl_intg_err 5.000s 120.006us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_regwen 2.000s 17.270us 1 1 100.00
csrng_csr_rw 2.000s 21.577us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 8.000s 377.735us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 92.000s 4983.484us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 5.000s 336.749us 1 1 100.00
csrng_err 2.000s 81.807us 1 1 100.00
csrng_sec_cm 2.000s 68.140us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 5.000s 336.749us 1 1 100.00
csrng_err 2.000s 81.807us 1 1 100.00
csrng_sec_cm 2.000s 68.140us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 5.000s 336.749us 1 1 100.00
csrng_err 2.000s 81.807us 1 1 100.00
csrng_sec_cm 2.000s 68.140us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 5.000s 336.749us 1 1 100.00
csrng_err 2.000s 81.807us 1 1 100.00
csrng_sec_cm 2.000s 68.140us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 5.000s 336.749us 1 1 100.00
csrng_err 2.000s 81.807us 1 1 100.00
csrng_sec_cm 2.000s 68.140us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 8.000s 377.735us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 5.000s 336.749us 1 1 100.00
csrng_err 2.000s 81.807us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 92.000s 4983.484us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 8.000s 377.735us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 5.000s 120.006us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 5.000s 336.749us 1 1 100.00
csrng_err 2.000s 81.807us 1 1 100.00
csrng_sec_cm 2.000s 68.140us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 5.000s 336.749us 1 1 100.00
csrng_err 2.000s 81.807us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 5.000s 336.749us 1 1 100.00
csrng_err 2.000s 81.807us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 5.000s 336.749us 1 1 100.00
csrng_err 2.000s 81.807us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 5.000s 336.749us 1 1 100.00
csrng_err 2.000s 81.807us 1 1 100.00
csrng_sec_cm 2.000s 68.140us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 5.000s 336.749us 1 1 100.00
csrng_err 2.000s 81.807us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 0.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:660) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*])
csrng_cmds 96275797424040887620596387878485712242641504183217713739963436062325032257743 130
UVM_INFO @ 127730628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job killed!
csrng_stress_all_with_rand_reset 89747570546812402660935371115003019799298391831433783890691251045879856089399 None