Simulation Results: edn/edn0

 
30/04/2026 15:30:31 DVSim: v1.33.0 sha: c776b8b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.88 %
  • code
  • 79.26 %
  • assert
  • 95.01 %
  • func
  • 80.36 %
  • line
  • 96.96 %
  • branch
  • 89.54 %
  • cond
  • 84.97 %
  • toggle
  • 76.46 %
  • FSM
  • 48.39 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.020s 60.551us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.940s 22.403us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.790s 22.098us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.630s 987.357us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.950s 17.352us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.270s 65.043us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.790s 22.098us 1 1 100.00
edn_csr_aliasing 0.950s 17.352us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.300s 95.757us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.300s 95.757us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.300s 95.757us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.000s 23.770us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.950s 46.609us 1 1 100.00
errs 1 1 100.00
edn_err 1.030s 51.673us 1 1 100.00
disable 2 2 100.00
edn_disable 0.740s 33.357us 1 1 100.00
edn_disable_auto_req_mode 0.990s 71.424us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.150s 68.700us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.780s 28.942us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.830s 28.569us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.050s 65.963us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.050s 65.963us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.940s 22.403us 1 1 100.00
edn_csr_rw 0.790s 22.098us 1 1 100.00
edn_csr_aliasing 0.950s 17.352us 1 1 100.00
edn_same_csr_outstanding 1.610s 79.425us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.940s 22.403us 1 1 100.00
edn_csr_rw 0.790s 22.098us 1 1 100.00
edn_csr_aliasing 0.950s 17.352us 1 1 100.00
edn_same_csr_outstanding 1.610s 79.425us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 11.600s 2776.088us 1 1 100.00
edn_tl_intg_err 2.090s 98.819us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.860s 61.427us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.950s 46.609us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 11.600s 2776.088us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 11.600s 2776.088us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 11.600s 2776.088us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 11.600s 2776.088us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.950s 46.609us 1 1 100.00
edn_sec_cm 11.600s 2776.088us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.950s 46.609us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.090s 98.819us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 57.210s 7210.610us 1 1 100.00