Simulation Results: edn/edn1

 
30/04/2026 15:30:31 DVSim: v1.33.0 sha: c776b8b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.81 %
  • code
  • 82.76 %
  • assert
  • 97.14 %
  • func
  • 77.52 %
  • line
  • 97.72 %
  • branch
  • 92.42 %
  • cond
  • 87.15 %
  • toggle
  • 94.48 %
  • FSM
  • 42.05 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.790s 30.359us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.870s 29.181us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.740s 41.595us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.280s 157.000us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.530s 20.089us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.280s 52.828us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.740s 41.595us 1 1 100.00
edn_csr_aliasing 1.530s 20.089us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 0.920s 46.445us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 0.920s 46.445us 1 1 100.00
genbits 1 1 100.00
edn_genbits 0.920s 46.445us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.920s 21.344us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.300s 96.386us 1 1 100.00
errs 1 1 100.00
edn_err 0.910s 23.914us 1 1 100.00
disable 2 2 100.00
edn_disable 0.760s 31.631us 1 1 100.00
edn_disable_auto_req_mode 1.350s 32.413us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.700s 304.016us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.760s 15.090us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.230s 23.418us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.360s 136.527us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.360s 136.527us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.870s 29.181us 1 1 100.00
edn_csr_rw 0.740s 41.595us 1 1 100.00
edn_csr_aliasing 1.530s 20.089us 1 1 100.00
edn_same_csr_outstanding 1.130s 124.691us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.870s 29.181us 1 1 100.00
edn_csr_rw 0.740s 41.595us 1 1 100.00
edn_csr_aliasing 1.530s 20.089us 1 1 100.00
edn_same_csr_outstanding 1.130s 124.691us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.620s 712.283us 1 1 100.00
edn_tl_intg_err 1.340s 62.759us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.810s 28.997us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.300s 96.386us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.620s 712.283us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.620s 712.283us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.620s 712.283us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.620s 712.283us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.300s 96.386us 1 1 100.00
edn_sec_cm 2.620s 712.283us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.300s 96.386us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.340s 62.759us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
edn_stress_all_with_rand_reset 30.280s 1867.297us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
edn_stress_all_with_rand_reset 79992352326870327792112420583958086354120894975038599185378288015228674807457 181
UVM_INFO @ 1867297178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---